I nvestigation of current collapse and recovery time due to deep level defect traps in β-Ga2O3 HEMT

R. Singh, T. R. Lenka, , R. T. Velpula, B. Jain, H. Q. T. Bui, and H. P. T. Nguyen

1Department of Electronics & Communication Engineering, National Institute of Technology Silchar, AS, 788010, India

2Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, 07102, USA

Abstract: In this paper, drain current transient characteristics of β-Ga2O3 high electron mobility transistor (HEMT) are studied to access current collapse and recovery time due to dynamic population and de-population of deep level traps and interface traps. An approximately 10 min, and 1 h of recovery time to steady-state drain current value is measured under 1 ms of stress on the gate and drain electrodes due to iron (Fe)–doped β-Ga2O3 substrate and germanium (Ge)–doped β-Ga2O3 epitaxial layer respectively. On-state current lag is more severe due to widely reported defect trap EC – 0.82 eV over EC – 0.78 eV, −0.75 eV present in Iron (Fe)-doped β-Ga2O3 bulk crystals. A negligible amount of current degradation is observed in the latter case due to the trap level at EC – 0.98 eV. It is found that occupancy of ionized trap density varied mostly under the gate and gate–source area. This investigation of reversible current collapse phenomenon and assessment of recovery time in β-Ga2O3 HEMT is carried out through 2D device simulations using appropriate velocity and charge transport models. This work can further help in the proper characterization of β-Ga2O3 devices to understand temporary and permanent device degradation.

Key words: β-Ga2O3; current collapse; degradation; HEMT; recovery time; traps; trapping effects

1. Introduction

There has recently been considerable interest in monoclinic β-phase of gallium oxide (β-Ga2O3) inspired by its excellent material characteristics—large energy bandgap EG~4.9 eV[1], high breakdown electric field EBrup to 8 MV/cm[2],and high electron velocity vsat~ 1.5 × 107cm/s[3]. Wide variety of intentional n-type dopants—Si, Ge, and Sn as shallow donors facilitate to achieve electron concentrations ~ 1 ×1020cm–3[4], although p-type doping in Ga2O3shows inconsistent findings[5,6]. Additionally, with the help of low-cost melt growth techniques, such as Czochralski[7], and floating zone[8],large size Ga2O3bulk substrate can be grown and thus offers cost competitiveness over other wideband semiconductors—GaN and SiC. The availability of low cost and large size β-Ga2O3bulk crystalline substrates further enables different epitaxial technologies, such as molecular beam epitaxy(MBE), and halide vapor phase epitaxy (HVPE) to grow Ga2O3with low crystal defects on native substrate. To compensate unintentional Silicon (Si) incorporation during growth of Ga2O3, deep level acceptors such as Mg, and Fe are used to achieve semi insulating bulk crystals[2], and controls substrate leakage. Out of the promising n-type dopants, Si, Ge,and Sn; Ge shows preferred choice for β-Ga2O3devices[4].

Several experimental studies on defects throughout the entire bandgap of β-Ga2O3(010) layers have used deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS) techniques[9–12]. Three distinct trap states at wC– 0.1 eV, 0.2 eV, and 0.98 eV in Ge-doped (010) β-Ga2O3grown using plasma assisted MBE[9], EC– 0.62 eV, 0.82 eV,1 eV in unintentionally doped (UID) (010) β-Ga2O3using edge-defined film-fed growth (EFG)[10], EC– 0.55 eV, 0.74 eV,and 1.04 eV[11]in β-Ga2O3crystal grown using Czochralski method, and two deep level traps at EC– 0.78 eV (due to Fe impurities) and EC– 0.75 eV (due to intrinsic defect)[12]in upper part of the bandgap with concentrations varying from 1014to 1016cm−3have been demonstrated.

With the distinct trap level defects reported so far, device performance can be easily questioned unless different trap sources and their individual effects on specific output parameters are fully established because device degradation may be reversible or permanent in nature. Significant progress in Ga2O3based electronic devices such as Schottky diodes[13], metal semiconductor FET (MESFET)[2], metal oxide semiconductor FET (MOSFET)[14,15], modulation doped FET (MODFET)[16], and HEMT[17]have been reported with good DC and RF performance, mainly due to Ga2O3excellent material properties.Traps in the device can affect thermal characteristics, including on resistance (Ron) and threshold voltage (VTh), a shift of 0.78 V in VThwas measured due to two distinct trap levels at 0.7 eV, and 0.77 eV in β-Ga2O3MESFETs on Fe-doped β-Ga2O3substrate[18]. Dynamic dispersion in drain characteristics led current lag due to trap at EC− 0.75 eV was demonstrated in back-gated Ga2O3based MOSFET[19].

Fig. 1. (Color online) Schematic cross sectional view of the analysed device structure.

Potential application of β-Ga2O3based devices beg the question of whether the device degradation due to various traps E – 0.98, 0.82, 0.78, 0.75 eV[9,10,12]is temporary or permanent in nature? In this work, we focus on traps originated from Fe-dopedβ-Ga2O3substrate, and Ge-doped epitaxial layer on Sn-dopedβ-Ga2O3substrate to model the reversible current collapse phenomenon along with measurement of current recovery time to its steady state value.

2. Device structure and simulation framework

Fig. 1 shows device structure of AlN/β-Ga2O3HEMT which is analysed in this report. The sequence of materials comprise of 25 nm AlN barrier layer on 2μmβ-Ga2O3substrate. Gate material of Au/Ni with gate length,LGof 0.25μm and Schottky barrier height of 0.8 eV is set by fixing the work function,ϕMof the gate metal of 2.2 eV, electron affinity of the AlN barrier is set as 1.4 eV[20]in material properties.Source/drain electrodes are considered to be perfectly Ohmic. The gate–source (LGS), gate–drain (LGD), and source–drain(LSD) spacing are 1.2, 2.95, and 4.4μm, respectively. Silicon nitride (Si3N4) insulator of 25 nm is used as surface passivation to suppress current collapse as per experimental device[2].

Using electron and hole effective masses ofβ-Ga2O3[21],total conduction band (NC) and valence band (NV) density of states of 3.6 × 1018and 2.86 × 1020cm−3, respectively, were calculated, and other parameters were considered from Ref.[17].

For undoped AlN layer default material parameters as mentioned in Ref. [22] are considered except electron affinity(χ= 1.4 eV). Due to low in-plane lattice mismatch between AlN/β-Ga2O3heterojunction, spontaneous and piezoelectric polarization built in model[22]is activated for AlN material region. A large conduction band offset (CBO), ΔEC= 1.75 eV[20]offers polarization induced sheet charge densityσ= 5.617 ×1013C/cm2[23]at the heterointerface due to sole polarization of AlN layer. In absence of p-type carriers,β-Ga2O3based devices are unipolar, so negative differential mobility model as given by Eq. (1) is chosen forβ-Ga2O3material region and default values of parameters[22]are replaced by mobility model[3]. The low-field electron mobility of 140 cm2/(V·s) as reported in Ref. [3] is in good agreement with Hall measurements electron mobility of 162 cm2/(V·s)[17].

Based on previous published reports[9–12], among the four electron trap levels—E1,E2,E3, andE4; the most prominent isE2and especially dominant in (01) sample, and the source of this trap level is intentional dopant Fe[12]. So to quantify the effect of Fe dopants led current collapse of drain current, theβ-Ga2O3substrate is doped with iron (Fe) as acceptor traps with energy levelEC–0.78 eV, and 0.75 eV[12].The Fe doping in the substrate has a Gaussian profile with peak concentration of 1018cm–3aty= 1.0μm, and gradually drops to 1016cm–3near the surface. In order to analyse the effect of traps, generated by commonly used n-type dopants,Ge inβ-Ga2O3epitaxial layer, three trap levels atEC−0.1 eV,−0.2 eV, −0.98 eV are uniformly doped in 50 nm buffer layer.In this case, the substrate is doped with n-type dopant (Sn)concentration of 1018cm–3to minimize the Fe effect in epitaxial layer as demonstrated in Ref. [9]. The stateEC–0.98 eV is also confirmed by Zhangetal.[10]asEC–1.0 eV by DLTS in Ni/β-Ga2O3Schottky diode on unintentional doped (UID)(010) substrate by edge-defined film-fed growth (EFG). All the trap levels are analysed in regard of current collapse phenomenon and are summarized in Table 1 with other characteristics. Only deep level traps with concentration ≥ 1015cm–3are considered.

3. Results and discussions

The proposed device is analysed under three different conditions—gate stress, drain stress, and gate–drain stress. In all three bias conditions, device is biased in low stress and high stress state for 0.1 to 1 ms with respective DC bias at the gate and drain terminals. During initial bias condition, the device is simulated for output drain current under DC bias at gate and drain terminal. After applying a DC bias ofVGS= 0 V andVDS= 5 V, this initial bias condition is maintained for 1 ms in dynamic mode. Then, the device is pulsed into high stress state, −25 V on the gate (in gate stress condition); 25 V on the drain terminal (in drain stress); and −25 to 25 V on the gate and drain terminals respectively for another 1 ms, as shown in Fig. 2. Then, the device is returned to its original bias condition. Since we are analysing the recoverable current collapse phenomenon which is not permanent in nature[24],in post-stress condition traps should gradually return to steady state occupancy state. To quantify the recovery time to steady state, bias condition is analysed for a longer time in the order of 105s in post stress condition. Fig. 3 shows current collapse phenomenon resulting of stress bias, as shown in Fig. 2. The drain current spikes momentarily to its maximum value corresponding toVGS= 0 V andVDS= 25 V and collapses at 2 ms. The trapping of electrons in deep level defects causes this undesirable effect and degrades the device performance.

To analyse the effect of these deep level traps under gate-stress condition, the drain bias remains at fixed bias of 5 V; the device is driven into pinch-off (high stress at gate–25 V for 1 ms) followed by steady state bias. The resulting drain current collapse and recovery time is shown in Fig. 4. It is evident that current degrades momentarily and almost full current recovery happens at timet= 2 ms.

Similar steps are performed to simulate the device under drain stress with appropriate drain and gate bias and the results are shown in Fig. 5. Due to the low concentration(1014cm−3) of deep level traps atEC− 0.1 eV, − 0.2 eV in Gedoped epitaxial layer there is no current collapse pheno-menon observed. In gate and drain stress bias conditions,both terminals are put in high stress for 1 ms with − 25 V at gate and 25 V at drain terminal. The results are shown in Fig. 6. Current collapse is evident mainly due to traps atEC–0.82 eV with recovery time of almost 10 min. The trap level atEC– 0.98 eV demonstrated in Ge-doped epitaxial layer contributes negligibly in current collapse, but steady state drain current restores after a time elapse of 1 h. The other two trap levelsEC– 0.75 eV, 0.78 eV show significant current collapse and recovery time of few seconds to few minutes are quantified respectively, the later one having large capture cross section of 10−14cm−2.

Table 1. Deep level traps reported in β-Ga2O3 substrate and epitaxial layer, energy level, capture cross section and trap concentration. Fe and Ge enabled current collapse and drain current recovery time to pre-stress condition.

Fig. 2. (Color online) Pre-stress and post-stress bias voltages at gate and drain terminals.

Fig. 3. (Color online) Pre-stress and post-stress drain current. Inset: current collapse.

Fig. 4. (Color online) Trapping and de-trapping of defect trap under gate stress.

Fig. 5. (Color online) Drain stress and recovery of current recovery due to de-population of traps.

Fig. 6. (Color online) Current collapse and recovery curve, showing intentional doped Fe causes most of the current collapse and Ge doping caused current collapse takes approximately 2 h to attain steady state value.

Fig. 7. (Color online) Ionised trap density horizontally at a depth of 0.5 μm in the substrate.

The ionized Fe trap occupancy before and after high stress bias condition highlights are shown in Fig. 7. It can be seen that the trap density under the gate and gate source area near the surface mostly affects the current degradation.Ionization trap density is plotted at a depth of 0.5μm from the surface in theβ-Ga2O3substrate. There is a significant difference in the occupancy of trap along the depth in the substrate and along the horizontal direction towards gate.The gate length of the analysed device, LGof 0.25 μm, and the effect of Fe trap occupancy extends along the depth up to 0.5 μm (two times of gate length), and along source and drain regions. Source, gate, and drain electrodes are shown in upper part of Fig. 7 to correlate device dimension with ionized trap density in the substrate.

4. Conclusion

The trapping effects led current collapse phenomenon using drain transient characteristics of β-Ga2O3HEMT is presented. The recovery time for the drain current to return to its steady state value is investigated using Atlas TCAD simulations. The trap level at energy EC– 0.8 eV in Fe-doped β-Ga2O3substrate plays crucial role in undesirable current collapse phenomenon and the recovery time is about 10 min. In the Ge-doped β-Ga2O3epitaxial layer, the trap level at EC–0.98 eV insignificantly degrades the drain current but takes roughly 1 h to restore the original value. This current degradation is reversible event and current returns to its steady state value but only after a finite time varying from few seconds to several minutes depending on the trap characteristics. It is also observed that unintentional interface traps have a negligible effect on current collapse. The report thoroughly establishes that intentional Fe-doping in semi insulating β-Ga2O3substrate led traps cause current collapse, and on the other side recovery time in current lag in Ge-doped β-Ga2O3epitaxial layer is approximately 1 h. By measuring the current recovery time, this report effectively distinguishes between temporary and permanent device degradation due to current collapse. The findings of this work may be useful in reliability study of β-Ga2O3devices.

Acknowledgements

This publication is an outcome of the collaborative R&D work undertaken in the project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology,Govt. of India, being implemented by Digital India Corporation.