Study on Device Characteristics of High-temperature Radiation-hardened SOI CMOS Process

ZHANG Qingdong, WU Jianwei, LI Jinhang, SONG Shuai, JI Xuming, GU Xiang, HONG Genshen, LI Bing

(1.School of Cyber Science and Engineering, Southeast University, Nanjing 210096, China; 2.The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214035, China)

Abstract: Because of the unique advantages of silicon-on-insulator (SOI) technology in both radiation and high temperature environments, it is meaningful to investigate the characteristics of SOI device with different top silicon film thicknesses (tSi), which will be of great value to further enhance the performance of high temperature radiation-hardened SOI complementary metal oxide semiconductor (CMOS) device. Firstly, a model of N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) is constructed and analyzed by process-level simulation. Based on the simulation data, actual devices with different tSi are manufactured by using 0.15 μm radiation-hardened SOI CMOS process that employs design and materials optimized for high temperature applications. The results indicate that both thin and thick tSi NMOSFET show approximate hardness performance under 150 krad(Si) total dose radiation, while the former has smaller leakage current at 225 ℃, making the NMOSFET with thinner tSi a better candidate for high-temperature electronics.

Key words：SOI NMOSFET; high temperature; radiation hardened; top Si film thickness

1 Introduction

Over the last few decades, silicon-on-insulator (SOI) technology has become a mainstream complementary metal oxide semiconductor (CMOS) technology due to its structural advantages in harsh environments such as space radiation and extreme temperature[1-3]. Compared with bulk Si, SOI introduces a buried oxide layer in substrate and has the property of full dielectric isolation, which makes it suitable for low power and radiation-hardened circuits because it is immune to latch-up and could offer smaller subthreshold slope, parasitic capacitances and charge collection volumes[4-6].

The leakage current of SOI device is several orders of magnitude less than that of bulk Si under high temperature as a result of the reduced p-n junction area[7-8], which makes SOI widely use in high temperature environment like aerospace, automobile and oil exploration[9-11]. By far, many studies have shown that top Si thickness affects all the electrical parameters of SOI device including threshold voltage (Vt) and saturation current (Idsat) under ambient temperature[12-13]. However, there is a lack of the research about the effect of top Si thickness on the SOI devices under high temperature, which will be of great importance to further enhance properties of high temperature SOI devices.

In this paper, we present an investigation on the SOI device characteristics under 25 ℃ and 225 ℃ with different top silicon film thicknesses (tSi) base on 0.15 μm radiation-hardened SOI CMOS process. The results could provide practical reference for the development of high temperature process technology and circuit design.

2 Experimental details

2.1 Device for simulations and experiments

The simulation of 5 V N-channel metal-oxide-semiconductor field-effect transistor(NMOSFET) devices with differenttSiwas carried out with technology computer aided design (TCAD). Top silicon film thickness (tSi) is 120 nm and 250 nm, buried oxide (BOX) thickness (tbox) is 400 nm, and doping concentration in the substrate under the BOX (Nsub) is 1×1015cm-3. The doping concentration of drain/source and gate are 1×1018cm-3. And the gate length and height are selected to be 500 nm and 250 nm, respectively. Then the actual 5 V NMOSFET devices are manufactured based on 0.15 μm radiation-hardened SOI CMOS process. Corresponding device characteristics are tested with Keysight B1500A semiconductor parameter analyzer.

2.2 Total ionizing dose experiments

The total ionizing dose (TID) experiment was conducted at60Co gamma irradiation facility. Main procedures are divided into testing before irradiation, device irradiation, irradiation monitoring and testing after irradiation. Related irradiation dose rate is 50 rad(Si)/s±10% and final irradiation dose reaches 150 krad(Si).

3 Results and analyses

3.1 Simulation results and analyses

In the first place, HT-SOI process development with TCAD simulation was researched, which could be used as a guideline for the actual process setup. The simulation conditions refer to the 0.15 μm radiation-hardened SOI CMOS process. According to the simulation results, while thin and thick Si film devices have the sameVt(0.95 V) at room temperature, there would be a huge difference onVtat high temperature. At 225 ℃, theVtof the thin Si film (tSi=120 nm) device decreases from 0.95 V to 0.62 V, while that of the thick Si film (tSi=250 nm) device decreases to 0.58 V. The device with thick Si film shows larger drift compared with the thinner one under high temperature.

For the thick Si film device, the threshold voltage can be expressed by formula (1). For the thin Si film device, depletion layer charge equals toqNAtSi/n(q,NA, andnare electron charge, doping concentration of p-type silicon, and carrier concentration, respectively). SoVtof the thin Si film device has less change than that of the thick Si film device. The simulation results accord with the theory.

(1)

Where,Vthis threshold voltage;Tis temperature;φFis Fermi potential;Coxis capacitance of gate oxide;kis Boltzmann constant;niis intrinsic carrier concentration;εSiis dielectric constant of silicon.

In addition, leakage current is a significant factor for HT device, which is the main cause of the failure of MOSFET device at high temperature. The equation of leakage current is shown in formula (2), which is proportional to the junction area (A)[14]. Based on the simulation structure, with the voltage applied to the drain being 0.1 V and 5 V, separately,voltage ranging from 0 V to 5 V is applied to the gate voltage, and the current in the drain is measured. According to the data collected, the drain current (Id) versus gate voltage (Vg) of NMOSFET device under 25 ℃ and 225 ℃ is shown in Fig.1. As shown in the inset figure of Fig.1, the device simulation structure with thin Si film has smaller junction area in comparison with the thick one. Furthermore, according to the simulation results (Fig.1), the leakage current of the device with 120 nm top Si thickness is 1748 pA/μm and the leakage current of the device with thicker device is 3 033 pA/μm at 225 ℃, which is in line with the theory analysis that the thinner device showed smaller leakage current.

(2)

Where,Ileakis leakage current of the channel;Dnis diffusion constant of electrons;τnis lifetime of electrons in the p-type neutral region;τeis effective lifetime;ωis the width of depleted area.

3.2 TID experiment results and analyses

Based on the simulation results, actual devices were manufactured to verify the simulation results and further analyze the effect of top silicon film thickness on the 5 V NMOSFET devices. The transmission electron microscopy (TEM) figure of device is shown in Fig.2a, and the device structure is H-type NMOSFET, as shown in Fig.2b.

Fig.1 Id-Vg curves of NMOSFET device under 25 ℃ and 225 ℃

Fig.2 TEM cross section (a) and device structure (b) of 5 V NMOSFET device

The TID effects of 5 V NMOSFET device under differenttSiwere researched, and theId-Vgcurves before and after 150 krad(Si) are shown in Fig.3. As can be seen from Fig.3, after the 150 krad(Si) radiation, theId-Vgcurve of devices with 120 nm and 250 nmtSidemonstrates similar results, that no apparent changes are shown in the curve compared with 0 krad(Si) radiation. Devices with differenttSiboth show outstanding TID radiation charac-teristic without extra device design, which could be attributed to the excellent irradiation properties of SOI device[15].

3.3 Device characteristics and analyses

The experimental plots ofId-Vgcurve under 25 ℃ and 225 ℃ operation temperature are shown in Fig.4. It is found that the electrical characteristics of the two devices show the same trend as the temperature changes, that is, theVtunder high temperature conditions shifts negatively compared to normal temperature, and the slope of the subthreshold characteristic curve decreases[16]. On the basis of the measurements, theVtchanges about 29.5% for the device withtSi=120 nm and about 35.1% for the device withtSi=250 nm while the temperature varies from 25 ℃ to 225 ℃. Meanwhile, theIdsatof the device withtSi=120 nm is reduced by approximately 21.9%, while the device withtSi=250 nm is reduced by approximately 19.3%.

Fig.3 Id-Vg curve before and after 150 krad (Si)

Fig.4 Id-Vg curve under operation temperature of 25 ℃ and 225 ℃

The variation trend reflected by the actual test data is basically consistent with the simulation results, detailed comparison data of which is listed in Table 1.

Table 1 Comparison between simulation and experiment of 5 V NMOSFET device characteristics

Further, the overall trend of 5 V NMOSFET device characteristics are researched, devices with differentVtare fabricated. TheVtis adjusted through the well implantation, ranging from 0.4 V to 0.8 V measured under the ambient temperature. The off-state current (Ioff)-Idsatcurve andIdsat-Vtcurve of 5 V NMOSFET under different operation temperatures (25 ℃ and 225 ℃) and top silicon film thicknesses (120 nm and 250 nm) are shown in Fig.5.

As shown in Fig.5a, under the ambient temperature, theIoffof 5 V NMOSFET with differenttSidisplayed no apparent disparities. The curve formed by black dots nearly overlapped with line consisted of blue upper triangles. However, under the high temperature of 225 ℃, 5 V NMOSFET with 120 nm top Si thickness shows smallerIoffthan that of 250 nm on the whole, which could be attributed to the smaller junction area of 5 V NMOSFET with 120 nm top Si thickness. At 25 ℃, theIoffof 5 V NMOSFET with 250 nm top Si thickness is 0.34 pA/μm. At 225 ℃, theIoffincreases to 917.3 pA/μm. While theIoffof 5 V NMOSFET with 120 nm top Si thickness only increases from 0.1 pA/μm to 512.5 pA/μm with the temperature increasing from 25 ℃ towards 225 ℃. Compared the thin silicon film device with the thick one, theIoffshows nearly two-fold difference at high temperature, which means higher power consumption.

Besides, theVtas a function of theIdsatcurrent is also researched, and theIdsat-Vtcurve is shown in Fig.5b. As shown in Fig.5b, theVt-Idsatcurve of 5 V NMOSFET devices with differenttSishows the similar and nearly overlapping curve, which means thattSidoes not have fundamental effect on theIdsat.

Fig.5 Ioff-Idsat curve and Idsat-Vt curve under different operation temperatures and top Si thicknesses

4 Conclusion

Under the irradiation and high temperature, devices with thin and thick top silicon film thicknesses take on different results. The result manifests that both the thin and thick silicon film devices meet the TID criterion of 150 krad(Si). Temperatures have much influence on theIoffandVt. According to the simulation and experiment results, it can be found that the thin top silicon film device has a better electricity characteristic than that of the thick one at 225 ℃, especially the leakage current, which will be of great benefits to the further development of low-power high temperature SOI devices.