Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

Jiancheng Zhang, Mao Ye,, Yiqiang Zhao and Gongyuan Zhao(1.Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, Tianjin University, Tianjin 300072, China; 2.Tianjin Infrared Imaging Technology Engineering Center, Tianjin 300072, China)

Bandgap references (BGRs) are widely used in digital, analog and mixed signal circuits, such as data converters, power management controllers, oscillators and phase locked loops (PLLs), because of their characteristics of low temperature coefficient (TC) over a wide temperature range. The accuracy of the voltage references plays a vital role in the performance of the whole chip.

The basic principle of BGRs is illustrated in detail in Ref.[1]. The reference voltage is acquired by adding a voltage proportional-to-absolute-temperature (PTAT) onto the base-emitter voltage that is complementary-to-absolute-temperature (CTAT). This approach restricts the temperature coefficient to a range of 20×10-6/℃-100×10-6/℃ with first-order curvature compensation[2]. A variety of compensation measures have been developed to improve temperature performance of the reference voltage produced by first-order BGRs. In Ref. [3], the reference voltage is achieved by superimposing two voltages which have curvature-up and curvature-down characteristics, respectively,which together obtain TC of about 4.2×10-6/℃. However, the technique above sacrifices chip area index resulting from the complex circuit structure. In Ref.[4], a high-order curvature-compensation technique of using metal-oxide-semiconductor (MOS) transistors operating in weak inversion region is presented, which achieves 4.5×10-6/℃. This method reduces chip area, while representing the characteristic of being vulnerable to process variation. Ref.[5] proposes a curvature compensation technique by utilizing different resistor characteristics, which is introduced in this work. However, the involvement of the large amount of resistance makes the whole bandgap reference circuit sensitive to process variation, causing the reference voltage and TC to deviate from the designed value. Process variation has become a great concern due to being difficult to solve.

This paper proposes a high-accuracy bandgap reference which employs two different types of resistors to realize a high-order curvature-compensation technique. The proposed BGR combines current-calibration and resistance-trimming techniques as process variation calibration method to help ease the impact of process variation to the accuracy, with respect to the TC and absolute value of reference voltage, respectively, which is not solved in Ref.[5]. The calibration structure realizes the output voltage scope of 0.49 V-0.56 V with TC of 9.45×10-6/℃-9.56×10-6/℃.

1 Proposed Architecture

1.1 Temperature characteristics of the base-emitter voltage VBE

The temperature behavior ofVBEis a key factor in the general bandgap reference circuits shown in Fig.1, which presents the characteristic of being complementary-to-absolute-temperature[6]. The bipolar junction transistor (BJT) is in the diode-connection mode, making the base-emitter voltageVBEexpressed as[7]

VBE=VGr(T0)+[VBE(T0)-VGr(T0)](T/T0)-
(η-α)VTln(T/T0)

(1)

Fig.1 Traditional bandgap reference

whereVGr(T0) is the bandgap voltage of silicon extrapolated at reference temperatureT0,ηis a temperature constant depending on both CMOS process technology and bipolar structure,andαis the order of the temperature dependency on the collector current. From Eq.(1), it can be indicated that the second term [VBE(T0)-VGr(T0)](T/T0) and the third term -(η-α)VTln(T/T0) are linear and nonlinear temperature dependent terms of the factorVBE, respectively. Therefore, it can be expanded in Taylor series as

VBE=β0+β1T+β2T2+β3T3+β4T4+…+βnTn

(2)

whereβ0,β1,β2…βnare constants representing corresponding temperature coefficients. The traditional BGRs described as Fig.1, which generally obtain TC in tens of 10-6/℃, are only able to eliminate the first-order terms ofVBE, leaving high-order factors to be corrected by means of high-order curvature compensation techniques. This work involves two types of resistors with opposite TCs to offset the nonlinear factors ofVBE. The calibration to both currents and resistors is introduced in this work as well to ameliorate performance of the reference voltage.

1.2 Module description

The proposed BGR shown in Fig.2 consists of main PTAT and CTAT loops, start-up circuits of corresponding loops, bias-yielding circuit, Ⅰ-Ⅴ convertor, current calibration and resistance-trimming loops.

Fig.2 Proposed BGR architecture

The reference currentIREFcan be roughly divided into three parts:IPTAT,ICTATandICORproduced by PTAT, CTAT and current calibration loops, respectively. The PTAT and CTAT loops are separated in such a way as being controlled independently in the current calibration loop, to ensure stability of the reference voltage over process, voltage and temperature (PVT). The resistance-trimming loop involves high-order curvature compensation by using two different types of resistors which have opposite temperature coefficients.

1.3 Produce of bandgap reference

This proposed BGR utilizes the superposition of PTAT and CTAT currents which are yielded by two independent loops to obtain a zero TC bandgap reference voltage, presented in Fig.2.

Both the PTAT and CTAT loops utilize one of the most useful characteristics of the operational amplifier (AMP), the huge gain, to keep the electric potential of the input ports equal. Therefore, voltageVBEis copied to the resistorR1, making the current flowing onR1become the currentIPTAT. By sharing a pnp BJT with PTAT loop to save the area of the chip, CTAT loop provides the currentICTAT, when leaving out the terms ofVBEhigher than third-order. Two types of currents are given as

Fig.3 Current calibration loop

(3)

(4)

wherenis the ratio of the area ofQ1andQ2. Both of the currents with opposite characteristics are mirrored in the current calibration loop, shown in Fig.3, to generate the correction current that is the combination of two different types of currents. Hence, the reference currentIREFis made up of these three parts described as

IREF=IPTAT+ICTAT+ICOR=
IPTAT+ICTAT+(rIPTAT+sICTAT)

(5)

wherer,sare considerably small factors needed for adjustment of the reference voltage when taking the influence of the manufacture process into account.

The proposed design can eventually get a reference current with proper TC satisfying the real condition, which may contain the mismatch as well as deviation of the resistance and supply voltage, by slightly adjusting the currentsIPTATandICTATrespectively. This type of current calibration loop that differs from conventional designs only involves fine tuning to regulate the performance,which does not make a significant change to the main part of the reference current.

The reference voltageVREFis generated when the reference current flows on the resistorsR3andR4. ResistorsR1,R2andR4are made up of high resistive poly resistors whileR3is implemented usingp-diffusion resistors. This elaborate design of distribution on the resistor type is aimed to compensate high-order temperature coefficients of the base-emitter voltageVBE. AssumeR1=R10(1+bT),R2=R20(1+bT),R4=R40(1+bT) andR3=R30(1+aT) represent the dependency of the resistance on the temperature, wherea,bare TCs of these two types of resistors, generally in the order of 10-3.R10,R20,R40andR30are the resistance at 0 ℃. Thus by using Taylor series and neglecting the influence of terms after the third-order it can be inferred that

(6)

As a result, the reference voltage is given as

(7)

In Eq.(7), the first-order termβ1ofVBEcan be offset by adjusting the ratio of corresponding resistance to set the first-order temperature coefficient ofVREFto zero. Correspondingly, the second-order factorβ2, and the third-order factorβ3ofVBEcan be cancelled by adapting the second-order and third-order temperature coefficients ofVREFto be equal to zero, respectively. The high-order compensated BGR is able to acquire excellent performance once properly regulating the resistance and the factorn.

1.4 Resistance-trimming technique

This paper brings in another novel calibration method towards process variation, i.e. resistance-trimming technique, to reduce the impact towards the value of reference voltage. The proposed technique avoids change to TC of reference voltage while performing resistance trimming. The reference voltage is regulated when keeping optimal TC which is changed in the meantime with output voltage in Ref.[5]. The resistance-trimming loop shown in Fig.4 utilizes a series of switches controlled by codeD7D6D5D4D3D2D1D0from a 3-8 decoder to decide how many resistors amongR51-R57are connected to the output circuit. ResistorsR50-R57shown in Fig.4 consist of two types of resistanceR3andR4. All the resistorsR51-R57are flowed over by reference currentIREF, but only a portion of them are connected to the output voltage port according to how well the output performance presents. When the codeD7D6D5D4D3D2D1D0changes from 0000_0001 to 1000_0000, resistorsR51-R57are connected to the output voltage port in turn, making the output reference voltage change from minimum to maximum.

This design that differs from conventional methods using only one type of resistance[5]realizes accurate and uniform adjustment without changing TC of the reference voltage. Every resistor among resistorsR51-R57includes two different types of resistance, high resistive poly andp-diffusion resistors. Therefore, the step of adjustment only changes the output value of the reference voltage without influencing TC once controlling the ratio of resistance ofR3andR4precisely.

The paralleling structure is able to realize a significantly small adjustment step compared to that without paralleling resistorR50because the step will reduce as resistanceR50decreases. This method is supposed to have the capability of achieving small adjustment by large resistance. In the meanwhile, it boosts layout match when utilizing large resistance.

Fig.4 Resistance-trimming loop

2 Experimental Results

2.1 Simulation results

The proposed high-order curvature-corrected BGR with process variation calibration technique has been implemented with 180 nm CMOS technology with its layout and the overall chip photograph exhibited in Fig.5. The simulation results of the temperature coefficient with regard to five process corners simulated with spectre have been shown in Fig.6. The temperature coefficient of the proposed BGR turns out to be 9.47×10-6/℃ over the temperature range of -40 ℃-120 ℃. The reference voltage is about 0.501 6 V with supply voltage of 3.3 V. The power supply rejection ratio is presented in Fig.7, from which we can infer that PSRR of the proposed BGR is 91 dB@100 Hz.

Fig.5 Layout and die photograph of proposed BGR

The simulation of resistance-trimming technique has been performed by changing the inputs of the 3-8 decoder. The regulation of the reference voltage is presented in Fig.8 with the output code turning from 0000_0001 to 1000_0000. The regulation to the reference voltage is uniform from the simulation results, making it convenient to approach design value. The current calibration loop adjusts the TC of the proposed BGR from 9.45×10-6/℃ to 9.56×10-6/℃. The combination of the current calibration and resistance trimming techniques effectively regulates TC and absolute value of the reference voltage in two aspects, greatly correcting the process variation as a result.

The proposed BGR is able to give sufficient freedom in terms of design margins according to process corner and Monte Carlo (MC) simulations in Fig.6 and Fig.9, respectively.

The temperature characteristic over the temperature range of -40 ℃-120 ℃ is simulated under five different process corners. It is observed that the temperature coefficient displays favorable consistency under different process circumstances.

Fig.9 presents MC simulation results over three different temperatures of -40 ℃, 27 ℃ and 120 ℃ in the form of histogram. The average reference voltage at 27 ℃ is 0.501 6 V with a standard deviation of 0.000 9 V, which is much closer to the design value compared to the other two conditions. It is suggested that about 99.7% of the reference voltage of all the three conditions locates in the voltage interval of 0.498 0 V to 0.504 0 V.

2.2 Test result

Fig.10 Measured temperature coefficients under three different supply voltages

Three different samples of the proposed BGR have been measured and characterized over the temperature range of -40 ℃-120 ℃ under three different supply voltages of 3.0 V, 3.3 V and 3.6 V, shown in Fig.10. The measured TC of the proposed BGR turns out to be 10.1×10-6/℃, which is slightly larger than the simulation result, which may result from the mismatch of the resistors in the layout, and the fact that the parasitical resistance of the transistors cannot be trivially neglected.The performance of current calibration and resistance trimming is not able to be measured because corresponding ports are not planned in the layout design restricted by area index.

Tab.1 compiles the performance comparison to other related works with all PVT. It can be seen that the proposed work has better performance in terms of temperature coefficient with respect to other state-of-art designs.

Tab.1 Comparison of performance with other related works

3 Conclusion

A low temperature coefficient bandgap reference circuit with novel manufacture process variation calibration circuit is implemented in 180 nm CMOS technology in this paper. It exhibits a measured temperature coefficient of 10.1×10-6/℃ over temperature range of -40 ℃-120 ℃ and a simulated power supply rejection ratio of 91 dB@100 Hz. The current calibration and resistance trimming techniques are simulated to change the voltage scope of 0.49 V-0.56 V with TC of 9.45×10-6/℃-9.56×10-6/℃. The proposed design satisfies such mixed signal systems, like AD converter, which require highly precise and PSRR reference voltage.

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