Design of IP core based on AMBA bus

JIA Boxiong， LI Jinming

(School of Instruments and Electronics, North University of China, Taiyuan 030051, China)

Abstract： With the rapid development of integrated circuit (IC) technology, reusable intelligent property (IP) core design is widely valued by the industry. Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture (AMBA), a design scheme of IP core is presented, and it is divided into the functional modules, and the structural design of the IP core is completed. The relationship between the internal modules of the IP core is clarified, and the top-down design method is used to build the internal architecture of the IP core. The IP core interface module, register module, baud rate module, transmit module, receive module, and interrupt module are designed in detail by using Verilog language. The simulation results show that the designed IP core supports serial peripheral interface (SPI) protocol, the function coverage of IP core reaches 100%, the maximum working frequency reaches 200 MHz, and the resource occupancy rate is less than 15%. The reusable IP core can support multiple data formats, multiple timing transmission modes, and master/slave operation modes, reducing the resource consumption of hardware circuits and having stronger applicability.

Key words： integrated circuit (IC)； intelligent property (IP) core； advanced microcontroller bus architecture (AMBA)； serial peripheral interface (SPI)

0 Introduction

Advanced microcontroller bus architecture (AMBA) specification is an on-chip interconnection specification for connecting and managing functional modules of the advanced risc machine (ARM) architecture[1]. ARM architecture processors are widely used in mobile Internet access devices, embedded devices, and multimedia devices, and the market scale is very large[2]. As a result, the AMBA bus is widely supported internationally, and has great potential to become an on-chip bus standard in the future. At present, AMBA bus specification which has been developed to version 4.0, defines three kinds of buses that can be used together, namely advanced high-performance bus (AHB), advanced system bus (ASB), and advanced peripheral bus (APB)[3]. As the mobile device market has entered the stage of explosive growth, ARM processors occupy more than 90% market share in the mobile device market due to its advantages of low power consumption, low cost and high performance. Because of its excellent performance, the AMBA bus has been adopted by ARM’s partners, attracting the attention of design companies at home and abroad, and has become the focus of on-chip bus research.

Serial peripheral interface (SPI) is a high-speed, full-duplex, synchronous communication bus that allows an embedded multi control unit (MCU) to exchange data with various external devices in a serial manner[4]. SPI protocol has the advantages of simple structure, less resource occupation and fast communication speed, and it has been widely used in embedded systems. Therefore, it is very important to design a general SPI intelligent property (IP) core. The IP core designed in this paper takes into account the actual application environment of engineering projects, and the designed IP core has strong programmability, wide application range and rich functions, which can meet most of the actual requirements of the design.

The on-chip bus has the advantages of simple structure, fast speed and flexible application. It can solve the communication problems such as data format, timing and communication among cores, which is convenient for system on chip (SoC) to integrate IP core. The on-chip bus provides various modes for SoC integration, including shared bus, multi-bus and point-to-point connection. Users can choose the proper connection mode according to bandwidth, power consumption, delay and other factors. Based on the research of the AMBA bus, the SPI IP core is designed for SOC chips. The hardware simulation based on FPGA verifies the performance of the IP core and the feasibility of a practical application.

1 SoC design and IP reusability technology

1.1 Design of SoC

SoC integrates systems on a single chip. Unlike previous IC, SoC integrates many very large scale integration (VLSI) systems on a single chip, thus providing complete electronic system functions. Currently, domestic and foreign academic circles generally define SoC as a chip that integrates control components (microprocessor, memory) and executive components (such as I/O, micro switch) on a single chip, and can work independently[5]. A common SoC architecture is shown in Fig.1.

Fig.1 SoC architecture

Compared with the past IC design methods[6], methodology is a new interdisciplinary research field with a wide range of technologies studied for the development of SoC design.

1.2 Reusability technology of IP core

IP core[7]refers to a reusable module provided by a party and verified by design that can realize a specific function[8]. The design is based on the IP core, as a designed unit module to call. IP core is generally divided into three types： hardcore, softcore and solid core. The main difference between them lies in the different delivery methods and implementation methods.

The reusable IP core is one of the core technologies of SoC[9]. The IP core usually adopts the parameterized design of the common but complex function modules in the circuit to design the reusable modules with adjustable parameters. Users can configure IP core parameters according to their requirements and generate register transfer level (RTL) codes to avoid repetitive work. To design a reusable IP core, it is necessary to have a system-level design scheme, which is used to describe the timing and function requirements of the IP core, as well as the source code or netlist files for the design and implementation of the IP core, as well as the simulation data to verify the design of the IP softcore. The design process is shown in Fig.2.

Fig.2 Design process of IP core

2 Structure of IP core

2.1 Design of top-level module

The basic function of the SPI IP core is to realize data transmission, that is, under the trigger of an asynchronous serial clock, according to the information configured by the user, serial send and receive data. Based on realizing the basic function of the SPI IP core, this paper extends the design appropriately[10].

According to the requirements of IP core design specifications, the external interface signals of the top module of the IP core include APB bus interface signals and SPI protocol interface signals. The designed module supports the data transmission interrupt request function, and can also be configured as a slave device. Therefore, the external interface signal of the top-level module should also have an interrupt request signal and host input signal when the module is configured as a slave device. When the module is configured as a slave device, the interface signals include host input clock signal ss_sck in slave mode, host input clock polarity signal OL and clock phase signal HA in slave mode and chip selection signal cs_in in slave mode. The design of top-level module of the SPI IP core is shown in Fig.3.

Fig.3 Diagram of top-level module

When the module works in the master mode, the connection between the master and slave is shown in Fig.4.

Fig.4 Connection diagram of IP core in host mode

When the module works in slave mode, the connection between the slave and master is shown in Fig.5.

Fig.5 Connection diagram of IP core in slave mode

2.2 Design of IP core

After completing the overall module design of the IP core, the top module of the IP core is divided into multiple functional modules according to the functional requirements, which is convenient for implementation. The internal module division of the IP core is shown in Fig.6.

In the module partition structure diagram, the interrupt signal includes all the signals output by the interrupt request module. Output signals include the chip selection signal cs_out output when configuring the master module and the output signal SDO of the sending module. Input signals include the chip selection signal configured as the slave machine, the clock polarity and clock phase signal of the slave machine, and the input signal SDI of the receiving module. The functional objectives of each functional module inside the IP core are as follows.

Fig.6 Allocation diagram of overall architecture

1) APB interface module, is mainly responsible for the communication between the APB bus and SPI module. It needs to decode APB bus signals so that the read and write commands of the APB bus can be correctly received and executed by the SPI module. APB interface module stores the address information of IP core registers, and controls the read and write of registers.

2) Register module, stores the important configuration information of IP core. The CPU can configure functions and control the status of the IP core through the register module. This module must be configured before the IP core is used.

3) Baud rate module, is configured as the master. When the chip selection signal is pulled down, it generates the baud rate clock and the effective edge signal of the baud rate clock required for SPI data transmission. When configured as slave, no baud rate clock is output, and the edge detection is carried out on the serial clock input by the host to generate an effective edge signal.

4) Send FIFO, which is a first in first out cache with configurable data depth and bit width. It is used to cache the data sent by the CPU through the APB bus until it is read out by the transmitting module, which can enable the CPU to write all the data transmitted at one time and improve the CPU work efficiency.

5) Receive FIFO, which is a first in first out cache with configurable data depth and bit width, is used to store the data sent by SPI slave until it is read out by CPU at one time through the bus.

6) Send module, which can be configured into SPI master slave mode, contains the master sends sub-module and the slave sends sub-module. When configured as the master, the host sending module is responsible for writing APB bus to send FIFO data readout and performing data-parallel transfer operation, and sending it to SPI slave machine according to SPI data transmission sequence. At this time, the slave sending module does not work. When configuring the slave machine mode, the slave machine sending module still needs to read out the data written into the FIFO and carry out the parallel transfer operation of the data. Then, under the trigger of the serial clock sent by the host, the slave machine sends the data to the SPI host by the SPI data transmission sequence.

7) Receiving module, can be configured as SPI master/slave mode, so the receiving module has both hosts receiving sub-module and slave receiving sub-module. When configured as a master, the host receiving sub-module converts the serial data sent from the SPI machine into parallel data, which is then written into the receiving FIFO so that the CPU can read the data through the APB bus. When configured as a slave machine, the slave machine receiving sub-module will convert the serial data sent by the host into parallel data and write it into the receiving FIFO under the trigger of the serial clock sent by the host.

8) Interrupt request module, is responsible for generating interrupt request signal in the process of data transmission. There are six kinds of the independent interrupt request signal, namely send FIFO air brake signal, send FIFO full interrupt signal, receive FIFO air brake signal, receive FIFO full interrupt signal, multi-master competition interrupt signal and master and slave configuration inconsistent interrupt signal. Interrupt request module will generate a comprehensive interrupt request signal, which is the result of the six interrupt request signal or logical operation and sends to the CPU.

2.2.1 APB interface module

The APB interface module is an important module for the connection between the IP core and the CPU[11]. The CPU can configure the IP core register information, write data, receive data, and read the status information in the register through the APB interface module. The APB interface module can define the address information of each register in the register module. CPU interface module can read and write operations of the corresponding register produced by writing data timing of APB bus according to the timing of sending FIFO to write data, also conforms to read the timing of the APB bus. The CPU can read data sequentially by receiving FIFO.

The APB interface module performs data writing operations mainly by sending the data written by the CPU to registers or FIFO. The timing diagram of the APB write operation is shown in Fig.7.

Fig.7 Timing of APB write operation

APB interface module performs read data transmission mainly by CPU reading data from register module or receiving FIFO. The timing sequence of the APB bus read operation is shown in Fig.8.

Fig.8 Timing of APB read operation

2.2.2 Baud rate module

Baud rate is a unit of symbol transmission rate, which represents the number of transmitted symbols per unit time. The unit is Bit per second (BPS)[12]. The means of frequency division is used by the designed IP core designed to obtain the baud rate used in transmission.

The baud rate module is responsible for receiving the system clock and finally generates the serial clock for SPI data transmission through the first-level frequency division with configurable coefficient and the second-level frequency division with fixed coefficient. The detailed frequency division flow chart is shown in Fig.9.

Fig.9 Two-stage frequency division flow of SPI

2.2.3 Data transmission module

The data sent by the CPU is first sent by the APB interface module into the sending FIFO cache[13]. After receiving the sending command, the sending module will read out the FIFO data, through the module’s internal processing of the data, according to the register configuration information, from high to low or from low to high in turn to send data. The FIFO depth is flexible and configurable. The processor can write all the data to be transmitted at one time, and the sending module will read the data one by one from the FIFO. It allows the CPU to process other tasks in parallel during the send, increasing productivity. The process diagram of the data sending module is shown in Fig.10.

Fig.10 Transmission of master data

2.2.4 Receiving module

The receiving module also has two sub-modules, namely the host receiving sub-module dl_master_rec and the slave receiving sub-module dl_slave_rec. When the SPI module works in master or slave mode, it is responsible for receiving data sent from peripherals, transiting and operating the received data in series, and storing it in the receiving FIFO for the CPU to read through the APB bus. The specific process of receiving is controlled by the state machine. The data receiving process diagram of the host receiving sub-module is shown in Fig.11.

Fig.11 Sub-module data of host receiving

2.2.5 Interrupt module

The function of the interrupt module is to generate an interrupt request signal when any data transmission error occurs, and send it to the CPU for processing, mainly to inform the CPU that there is a problem in the process of data transmission[14]. The interrupt module can generate six kinds of independent interrupt request signals and one integrated interrupt request signal which is not shielded in SPI IP core design.

3 Verification of module

3.1 Register module

Register module is an important function module in IP core, which stores the control information of IP core data transmission[15]. The incorrectness of the function of the register module will directly lead to the error of the whole function of the IP core, so it is very important to verify the correctness of the function of the register module. There are mainly two kinds of test tasks for the simulation verification of the register module. One is the reset test. After the system is reset, verify whether the register group is back to the initial value. The second is the basic read and write register test, through the APB interface module write data, read data, verifying whether the IP core internal register can be read and written correctly. After the reset, the initial register values in the register module meet the design requirements, and the reset test passes. The APB interface module writes data to registers. After this operation, the APB interface module reads data to check whether the read and write data is consistent. The random sequence generated by the system function random was used to verify the module’s insensitivity to data and improve the completeness of the test. The simulation results of the register module are shown in Fig.12.

Fig.12 Register module simulation results

3.2 Baud rate module

When SPI sends and receives data, the master and slave computers need to know each other’s baud rate configuration. Data can be sent and received only when the master and slave computers have the same baud rate configuration. Generation of baud rate is also a key function of IP core. The main function of this module is to divide the input APB system clock and output the serial clock sck, which serves as the clock signal of data transmission between master and slave computers.

In addition, another function is to generate effective signals sck_riseedge and sck_falledge of baud rate clock, which is used to control the data sampling and output of master and slave machines. The simulation of the baud rate module is shown in Fig.13.

Fig.13 Baud rate module simulation results

3.3 Practicability verification of IP core

After the design of each module is completed, the IP core needs to be placed in a real hardware environment for practicability verification. FPGA simulation is close to the system environment of practical application, and chip simulation can provide excellent performance, and it has the advantages of programmability, low cost, fast speed, easy commissioning, and so on. Based on these advantages, hardware simulation means is adopted based on FPGA tools. After synthesis, resource consumption report, time sequence report and power consumption report are given.

Through the analysis of the report, it can be seen that the designed IP core occupies a small number of resources, occupying less than 15% of the board’s resources. The timing report indicates that the maximum clock frequency of the IP core can reach 200 MHz, which can well meet the needs of various designs. IP core power consumption is low, its performance can be better. The logical resource consumption report, power consumption report and timing report are shown in Figs.14-16.

Fig.14 Report of logical resource consumption

Fig.15 Report of power consumption

Fig.16 Report of timing

4 Conclusions

Based on the research of AMBA bus and related protocols, a reusable IP core is designed, the designed IP can support both APB and SPI protocols through simulation verification, its maximum working frequency reaches 200 MHz, and the resource occupancy rate is less than 15%. The interface module, register module, baud rate module, transmit module, receive module and interrupt module are designed well. In addition, the transfer bridge is encapsulated in the IP core, and the baud rate module is designed by a two-stage frequency division algorithm. Not only improve CPU efficiency but also reduce the resource consumption of hardware circuits.