Non-PLL high-precision synchronous sampling method among lots of acoustics acquisition channels for underwater multilinear array seismic exploration system

JIANG Jiajia， CUI Jindong， WANG Xianquan， LI Xiaodong， ZENG Xianjun，ZHOU Dasen， YAO Qingwang, DUAN Fajie， FU Xiao

(1. State Key Lab of Precision Measuring Technology and Instruments， Tianjin University， Tianjin 300072， China；2. Beijing Dynamic GeoSolutions Co. Ltd.， Beijing 100107， China；3. Guangzhou Marine Geological Survey， Guangzhou 510075， China)

Abstract： Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node (AN) samples analog signals by its own analog-digital converter (ADC). Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system, an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop (PLL) is built, and a high-precision synchronous sampling method is proposed, which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock. Based on the improved synchronous sampling model, the influence of clock stability, transmission delay and phase jitter on synchronous sampling error is analyzed, and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed. The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle, and compensate the influence of signal transmission delay on synchronous sampling error. At the same time, it greatly reduces the complexity of software and hardware implementation of synchronous sampling, and solves the problem of long locking time after changing the sampling rate in traditional methods. The experimental system of synchronous sampling for dual linear array is built, and the synchronous sampling accuracy is better than 5 ns.

Key words： seismic exploration system； synchronous sampling； non phase locked loop (PLL)； local clock asynchronous drive； transmission delay

0 Introduction

The distributed data acquisition system is widely used in seismic exploration, oil and gas exploration, towed sonar and other fields[1]. Underwater seismic exploration system is a special distributed seismic data acquisition system, which requires array signal processing[2]and seismic data inversion[3-5]based on high-precision synchronization among different channels[6-7]. Therefore, each channel in each acquisition node (AN) of the system needs to maintain a high-precision synchronous sampling[8-9].

Several solutions have been proposed to achieve synchronization sampling in the distributed data acquisition system, such as IEEE1588 precision time protocol (PTP) and GPS synchronization method. The synchronization accuracy of IEEE1588 PTP is relatively low, and the synchronous sampling error reaches the sub-microsecond level[10-12]. The synchronous sampling error of GPS synchronization method is small (about tens of nanoseconds), but this method is not suitable for underwater seismic exploration system for the radio wave signal cannot be transmitted underwater[13-15].

In addition, several synchronization sampling methods have also been presented to decrease the error of the underwater seismic exploration system. Ref.[16] uses clock data recovery technology and traditional PLL to realize synchronous sampling in all ANs, and uses logic delay compensation to eliminate the synchronization delay error of master clock[16]. The distributed AN extracts and recovers the master clock from the data stream, then uses the recovery clock and the traditional non phase locked loop (PLL) to drive all channels to sample synchronously. This method requires additional hardware circuit design, which increases the circuit design complexity and system cost. The increased complexity of hardware circuit also adds additional fault points to the system.

Based on the master slave synchronous sampling model, Jiang[17]proposed a high-precision analog PLL for multi-channel signal synchronous acquisition, which is different from the traditional PLL. The Σ-Δ analog-digital converter (ADC), the core of the AN, is placed in the closed-loop feedback link as a frequency divider, aligning the master clock and slave clock at the same time to realize the high-precision multi-channel signal synchronous acquisition. However, this PLL uses voltage-controlled temperature-compensated crystal oscillator (VCTCXO) with small adjustable range to adjust the PLL frequency. When the sampling rate is switched, the locking time of PLL is long. The single locking time can be several seconds or even more than ten seconds. Therefore, this method is only suitable for fixed sampling rate, but cannot realize resynchronization of the sampling rate. In addition, the method reduces the synchronous sampling error caused by phase jitter with increasing the transmission delay, but cannot completely eliminate the effect of phase jitter in principle.

Li et al.[18]proposed a high-precision synchronization method with variable sampling rate on the basis of Jiang[17]. By sending different commands and synchronization clocks, and changing the configuration of the improved PLL and ADC according to the commands, the node sampling clock is synchronized with the variable synchronization clock, and the resynchronization sampling with variable sampling rate is realized. This method reduces the locking time of resynchronization when the sampling rate changes, but the locking time is still at the millisecond level.

In view of the limitation of traditional synchronous sampling technology, we construct an improved model of high-precision synchronous sampling based on the master-slave synchronous model and local clock asynchronous drive with non PLL, and propose a high-precision synchronous sampling method which combines the short-term stability of node local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock. It greatly reduces the hardware and software implementation complexity of synchronous sampling, and solves the problem of long locking time after the traditional method changes the sampling rate. The main contributions are as follows:

1) Based on the master-slave synchronous model, an improved model of high-precision synchronous sampling with non PLL local clock asynchronous driving is constructed, which effectively eliminates the influence of phase jitter on synchronous sampling error in principle.

2) The influence of clock stability, transmission delay and phase jitter on synchronous sampling error is analyzed to support the design based on high-precision synchronous sampling method.

3) A high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed, which effectively compensates the influence of signal transmission delay on synchronous sampling error.

1 Structure of underwater multilinear array seismic exploration system

Underwater multilinear array seismic exploration system is mainly composed of onboard acquisition recording system (ARS) and underwater acoustic detection streamers. Each acoustic detection streamer contains a large number of ANs, as shown in Fig.1. The ARS sends various messages to the ANs in each streamer through the wired downlink transmission medium. ANs convert the analog signal collected by hydrophone into digital signal through Σ-Δ ADC, and send it to the ARS for data processing and storage.

Fig.1 Underwater multilinear array seismic exploration system

2 Synchronous sampling model

The improved high-precision synchronous sampling model based on asynchronous driving of local clock with non PLL is shown in Fig.2. The synchronous sampling model improves the traditional master-slave synchronous sampling model, which uses clock data recovery and PLL technology to recover the master clock in the ANs and synchronizes the ADC driving clock with the master clock through PLL technology. Our model uses the local clock of the AN to drive Σ-Δ ADC sampling, sending the master clock as a periodic calibration signal to synchronize the local clock to achieve synchronous sampling. In this study, the master clock is named synchronous calibration clock (SCC),fc.

Fig.2 Synchronous sampling model based on asynchronous driving of local clock with non PLL

The SCC is sent to each AN by the ARS. The network time protocol (NTP) server of the ARS outputs 10 MHz clock signal, which is input into the SCC module to generate the SCC by frequency division for synchronization of the driving clock of each ADC of AN. The ARS sends synchronization command to control the synchronization of all ADCs in the ANs at the same time.

The SCC and synchronization command are sent to forwarding node FN(1) at a distance of wired downlink transmission mediumla, and then forwarded by FN(1) to the next FN at a distance oflb, and then transmitted to the first AN of the current streamer at a distance oflc, and then received by each AN of the current streamer in turn. At last, all the ANs receive the SCC and synchronous command. There are equalizer and driver in FNs and ANs, which are used to receive and send SCC and synchronous command. Equalizer and driver constitute information receiving interface module and information sending interface module, respectively.

Each AN has a local clock with high short-term stability to control the operation of the AN. A synchronous processing module is set inside the AN to receive the SCC and synchronous command. The synchronous processing module generates the ADC driving clock. According to the SCC received by the information receiving interface module, the ADC driving clock is synchronously calibrated. At the same time, the synchronous event is sent to the ADC according to the synchronous command to further synchronize the conversion process of all ADCs. Compared with Refs.[16-18], this study does not use PLL to align the master-slave clock, but uses the master clock (SCC) to calibrate the driving clock of ADC periodically. After the sampling rate changes, there is no need to go through a long locking time[15-16], and no need to reconfigure the PLL and ADC[17]. The next SCC cycle can complete the resynchronization.

Next, we will describe the design and implementation of the key modules in the proposed synchronous sampling model, including the generation and transmission of SCC and the design of synchronous processing module.

2.1 Generation and transmission of SCC

The NTP server will output 10 MHz clock signal, and input them into the SCC module. In the SCC module, the SCC is generated by frequency division of 10 MHz, and the satellite timing signal reference is introduced outside the NTP server to calibrate the 10 MHz clock signal. The ARS sends the SCC to the subsequent FNs and ANs through the driver, and the equalizer on the ANs receives the SCC.

2.2 Design of synchronous processing module

The schematic diagram of synchronous processing module is shown in Fig.3. The synchronous processing module mainly includes ADC driving clock generation module and synchronous event sending module. The synchronous processing module receives SCC and synchronous command. The SCC is input into ADC driving clock generation module to calibrate ADC driving clock. At the same time, it is input into synchronous event sending module, cooperating with synchronous command to generate the ADC synchronous event.

Fig.3 Schematic diagram of synchronous processing module

Fig.4 shows the generation principle of ADC driving clock. The AN first multiplies the local clockflthrough the frequency multiplier in the node to generate a high frequency clock signalfh(multiplier coefficient isM). Then the frequency divider is used to divides the high frequency clockfhto generate the ADC driving clockfw(divider coefficient isN). The relationship betweenfwand local clockflis

(1)

Fig.4 Schematic diagram of ADC driving clock generation

The ADC clock is periodically calibrated by SCC, as shown in Fig.5, and the calibration cycleTc=1/fc. When the AN receives the SCC, the ADC clock is calibrated at the rising edge of the SCC, so that the rising edge of the ADC clock and the SCC are aligned. It means that the frequency difference of ADC clock is corrected every timeTcto eliminate the influence of clock stability on synchronous sampling error.

Fig.5 Schematic diagram of synchronous calibration

As shown in Fig.6, it is the waveform diagram of the synchronous event sending module. In the synchronous event sending module, after receiving the synchronous command, the synchronous event is sent at the next rising edge of the SCC, so that all ADCs in the ANs can sample synchronously.

Fig.6 Schematic diagram of synchronous event sending module

3 Error analysis

Although an improved master-slave synchronous sampling model is proposed, a high-precision synchronous sampling result cannot be obtained only by this synchronous sampling model. In the following section, we will analyse the influence factors of synchronous sampling error in detail.

3.1 Clock stability

The local clock of the AN is the clock whose output frequency isfl. But the crystal oscillator output frequency has the problems of drift and aging, there is a certain output frequency difference between the local clocks in different ANs. When the underwater multilinear array seismic exploration system works continuously for a long time, the frequency difference will gradually accumulate, resulting in a cumulative clock error of the system, and the ADC conversion process between ANs cannot be synchronized. The stability of crystal oscillator frequency is very important to the performance of seismic exploration system. The stability of crystal oscillator output frequency is affected by many factors, such as temperature, voltage, load and aging. In most cases, the influence of temperature on the stability of crystal oscillator output frequency is greater than that of other factors[19]. Temprature-compensated crystal oscillator (TCXO) is selected for the local crystal oscillator of each AN, which can compensate the frequency drift caused by temperature and improve the stability of local clock. The crystal oscillator used in NTP server is oven-controlled crystal oscillator (OCXO), which is controlled and tamed by satellite timing signal reference to provide 10 MHz clock synchronization signal.

The frequency stability of the 10 MHz synchronous clock output from the NTP server OCXO is ±2×10-9Hz, and the TCXO frequency stability of the AN is ±2×10-6Hz. Although the clock frequency stability of OCXO and TCXO output is high, there are still some clock cumulative errors, as shown in Fig.7.

The maximum time difference of two identical crystal oscillators in one second is calculated by

(2)

It can be seen from Eq.(2) that for the OCXO with 10 MHz output frequency, the frequency stability is ±2×10-8Hz, and the maximum clock cumulative error of 2 ns occurs in 10 MHz clock signal per second. It also means that the maximum clock cumulative error of 2 ns occurs in SCC per second, which meets the accuracy requirements of synchronous sampling. For TCXO with output frequency of 16.384 MHz, the frequency stability is ±2×10-6Hz, and the maximum time difference between two ANs is 4 μs. It also means that the maximum time difference of ADC driving clock in one second is 4 μs, which cannot meet the accuracy requirements of synchronous sampling. After the master-slave synchronous calibration, the maximum time difference of ADC clock in the synchronous calibration time (Tc) is 0.062 5 ns, which meets the accuracy requirements of synchronous sampling. Therefore, we propose a high-precision synchronous sampling method which combines the short-term stability of local asynchronous driving clock and the master-slave synchronous calibration of local sampling clock to effectively reduce the synchronous sampling error.

3.2 Transmission delay

The SCC is sent to each AN through category 6 (Cat-6) twisted pair transmission lines. Due to the different distance among the ARS and different ANs, each AN receives the SCC with transmission delay. As shown in Fig.8, the time difference between the SCC in the ARS and the SCC received by AN(i,j) which represents the transmission delay of SCC from the ARS to the AN(i,j), and the transmission delay is defined as Δti,j(i=1,2,…,n；j=1,2,…,m). Due to the transmission delay of SCC, the synchronization error exists in ADC driving clock generated by each AN, which cannot achieve high-precision synchronous sampling.

Fig.8 Schematic diagram of transmission delay

3.3 Phase jitter

In Ref.[17], the seismic data are sent and uploaded at the falling edge of the masterclock[17]. Due to the phase jitter between the signals of DRDY (data ready) and master clock, the relationship between the two signals is uncertain. When the falling edge of the DRDY is prior to the falling edge of the master clock (Δti,j≤Δts), the data sent at the falling edge of the master clock are the converted data at the current sampling time； When the falling edge of DRDY precedes the falling edge of synchronous reference signal (Δti,j>Δts), the data sent at the falling edge of master clock are the converted data at the next sampling time. Therefore, the phase jitter of the signal may lead to a synchronous sampling error of one sampling period[17]. Fig.9 shows the synchronous sampling error caused by phase jitter.

The synchronization method adopted in this study is to send and upload the converted data after 24 ADC driving cycles after the DRDY is pulled down. Therefore, the error caused by the phase jitter is only the phase jitter itself, which will not cause the error of a sampling cycle, and the phase jitter is generally at the picosecond level. Considering this, the proposed synchronous sampling model and method can ignore the error caused by phase jitter.

Fig.9 Schematic diagram of synchronization error caused by phase jitter

As have discussed above, we analyze the influence of clock stability, transmission delay and phase jitter on synchronous sampling error. The synchronous sampling model constructed in this study can effectively eliminate the impact of clock stability and phase jitter on synchronous sampling error, but cannot eliminate the synchronous sampling error caused by transmission delay.

4 High-precision calibration method of synchronous sampling error

In order to correct the synchronous sampling error caused by signal transmission delay, we propose a high-precision synchronous sampling error calibration method based on step-by-step compensation of transmission delay. The idea of this calibration algorithm mainly includes two steps: signal transmission delay estimation, and signal transmission delay compensation.

Firstly, the signal transmission delay is estimated. Due to the large number of ANs in underwater multilinear array seismic exploration system, the measurement of transmission delay among ANs is very complex. Therefore, a simple transmission delay estimation method is proposed.

It can be found that the main reasons for the delay in the process of signal transmission include: the transmission delay generated by the signal through the AN, and the transmission delay generated by the signal through the transmission line. Therefore, the total delay in signal transmission can be estimated as

Δtij=(i+j)(td+tr)+te[la+(i-1)lb+jlc],

(i=1,2,…,n;j=1,2,…,m),

(3)

where Δtijis the delay time between the ARS and the AN(i,j);tdis the transmission delay of the signal sending interface;tris the transmission delay of the signal receiving interface;teis the transmission delay of the transmission line per meter;lais the distance of the transmission line between the ARS and FN(1);lbis the distance of the transmission lines between the FNs;lcis the distance of the transmission line from the FN to the AN; andldis the distance of the transmission line between the ANs.

At the same time, we can get

tij,gh=[(g-i)+(h-j)](td+tr)+te

[(g-i)lb+(h-j)lc],

(i,g=1,2,…,n；j,h=1,2,…,m),

(4)

wheretij,ghis the transmission delay between the AN(i,j) and the AN(g,h).

From Eq.(4), we can find thattij,ghis related toi,j,g,h,td,tr,te,lbandlc, wherei,j,g,h,lbandlcare variables andtd,trandteare constants. The signal transmitting and receiving interface chip selected in this study has a precise fixed transmission delay,tdandtrare known,tecan be calculated by actual measurement,lbandlcare also determined in a specific system. Therefore, we can calculate the estimated transmission delay between the AN(i,j) and the AN(g,h) by Eq.(4).

Fig.10 Schematic diagram of transmission delay error elimination

Then we compensate the signal transmission delay. A transmission delay compensation module is set in the AN(i,j). The delay compensation module generates a delay oftij,nmfor the SCC received in the AN. After the corresponding delay compensation for all ANs, as shown in Fig.10, the synchronization error caused by the transmission delay is corrected, The rising edge of SCC of all ANs is at the same timetnm, and the rising edge of driving clock of all ADC is at the same time, which realizes the synchronous sampling of all ANs.

5 Discussion

1) The traditional synchronization method uses the clock data recovery technology to extract and recover the master clock from the data stream, and uses the recovered master clock to drive ADC synchronous sampling. The clock data recovery technology needs to design additional circuit modules to achieve the corresponding functions, and also needs to carry out data encoding and decoding. When designing the clock data interface, we need to consider the transmission jitter,which will lead to complex design. With our method, the master clock is used to calibrate the local crystal oscillator periodically, instead of designing the clock data recovery module, which reduces the design complexity of software and hardware and reduces the system cost.

2) The traditional synchronization method uses PLL to synchronize the recovered master clock with the working clock of ADC to realize synchronous sampling. PLL realizes synchronization by comparing the phase of the reference signal with the local crystal oscillator, and continuously adjusts the phase of the output clock according to the phase of the reference signal until the two signals are synchronized. In order to ensure the stability of the output clock, the VCTCXO with small adjustable range is selected as the local crystal oscillator in the traditional synchronization method. When the sampling rate is changed, the locking time of the PLL will be very long, and the locking time can reach several seconds. Therefore, the traditional synchronization method mainly focuses on the synchronous sampling with a fixed sampling rate. In this study, an improved model of high-precision synchronous sampling based on local clock asynchronous driving with non PLL is proposed, which overcomes the limitation of fixed sampling rate. By combining the short-term stability of node local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock, the resynchronization of variable sampling rate can be completed only in a synchronous calibration cycle of a few milliseconds after changing the sampling rate.

3) The traditional synchronization method cannot eliminate the effect of phase jitter on synchronous sampling error in principle, and phase jitter may produce a synchronous sampling period error. It also uses delay compensation method to reduce the effect of phase jitter, but the delay compensation method will increase the difficulty of system design, and the delay compensation method is more complex. The synchronous sampling model and method constructed in this study realizes the immunity of synchronous sampling error to phase jitter in principle, and reduces the difficulty of design.

6 Experiment

In order to verify the validity of the synchronous sampling model and calibration method, we set up an experimental system, including two streamers with two ANs on each streamer, as shown in Fig.11.

Fig.11 Schematic diagram of transmission delay error elimination

In Fig.11, the distancelabetween the ARS and the FN(1) is 100 m, the distancelbbetween the FNs is 50 m, the distancelcand the AN is 50 m, and the distanceldbetween the ANs is also 50 m. Each AN contains 24 signal acquisition channels. The local crystal oscillator of the AN is the TCXO whose output frequencyflis 16.384 MHz, and the nominal frequency tolerance of the crystal oscillator is ±2×10-6Hz, with high stability. In order to ensure that the synchronous sampling accuracy is not less than 10 ns and the synchronous reset clock signalfcis not less than 40 kHz, 64 kHz is selected. The high-frequency clock signalfhoutput by multiplier in the AN is 327.68 MHz, and the driving clockfwof ADC is 4.096 MHz.

6.1 Generation of ADC driving clock

First, we verify the generation process of ADC driving clock. Fig.12 shows the driving clock waveform of ADC of the 12th acquisition channel in AN(2,1).

Fig.12 Waveform of ADC driving clock

6.2 Comparison between calculated value and actual measurement value of transmission delay

Firstly, the transmission delay per unit length(1 m) is calculated by measuring the transmission delay from the ARS to FN(1). The transmission delaytdof signal transmission interface and transmission delaytrof signal receiving interface are 20 ns, and the distance between the ARS and FN(1) is 100 m. It is measured that the transmission delaytfrom ARS to FN(1) is 498 ns. Therefore, we can calculate the delay of the unit length transmission line to the signal iste=(t-td-2tr)/la=4.58 ns.

Through actual measurement, the actual transmission delays Δt1, Δt2and Δt3are obtained: Δt1=272 ns， Δt2=267 ns, and Δt3=539 ns, as shown in Fig.13.

From Table 1, it can be seen that the error between the actual transmission delay and the estimated transmission delay is less than 5 ns, which verifies the accuracy and effectiveness of the signal transmission delay estimation.

Table 1 Estimated and measured values of transmission delay

Fig.13 Actual measured values of transmission delay

Finally, we measure the SCC after compensation, and the result is shown in Fig.14. After compensation, the transmission delay error of SCC of each AN is less than 5 ns.

Fig.14 SCC after compensation

6.3 Measurement of synchronous sampling error

The synchronous sampling error can be obtained by measuring the time difference of DRDY of ADC of different ANs. As shown in Fig.15, there are output signals of the 10th channel DRDY in AN(1,1), AN(1,2), AN(2,1) and AN(2,2), respectively. It can be seen from Fig.13 that the synchronous sampling error is less than 5 ns.

Furthermore, we test channels 31, 32, 33, and 34 to verify the synchronization. Through synchronous calibration and error compensation on different channels, the synchronous signals can be displayed on the software interface, as shown in Fig.16.

Fig.15 The 10th channel DRDY output signals in AN (1,1), AN (1,2), AN (2,1) and AN (2,2)

7 Conclusions

This paper presents a simple and effective synchronous sampling method to ensure the synchronous operation of different ANs in underwater multilinear array seismic exploration system. Firstly, an improved high-precision master-slave synchronous sampling model based on master-slave synchronous model and local clock asynchronous drive with non PLL is constructed as the physical structure and the basis of the proposed synchronous sampling method. Based on the synchronous sampling model, a simple synchronous sampling method is proposed, which uses the short-term stability of the local asynchronous clock of the AN to generate the ADC driving clock. And the master clock SCC periodically calibrates the ADC driving clock to achieve fast resynchronization with variable sampling rate. The influence of clock stability, transmission delay and phase jitter on synchronous sampling error is analyzed, and an error calibration method is proposed to compensate the transmission delay step by step. The experimental results are consistent with the theoretical analysis, which proves the effectiveness of the proposed synchronous sampling method. Based on the proposed synchronous sampling method, the software and hardware complexity of underwater multilinear array seismic exploration system is greatly reduced, and the synchronous sampling error can be reduced to less than 5 ns, which is obviously superior to the existing synchronous sampling methods.