氧化型垂直腔面发射激光器的常见失效模式和机理分析

张玉岐，左致远，阚 强，赵 佳,4

（1.山东大学 激光与红外系统集成技术教育部重点实验室，山东青岛 266237；2.厦门市三安集成电路有限公司，福建厦门 361000；3.中国科学院半导体研究所，北京 100083；4.山东大学 信息科学与工程学院，山东青岛 266237）

1 Introduction

Vertical Cavity Surface Emitting Lasers (VCSELs) are one of the most popular types of semiconductor lasers, and have a wide application range in the industry.It has the advantages of a low threshold, low power consumption, easy fabrication,high rate and low cost, and has become the core light source for short-range fiber optics data communications and optical sensing[1-4].Most of them use GaAs/AlGaAs materials operating at 850 nm.

Reliability is a key indicator of long-term use of semiconductor lasers and is very important for applications, and is the core problem of device development, design, fabrications and application[5-6].VCSELs had a field failure rate of ＜10 ppm/year over the past decade, thanks to the improvement of its design capacity and technological level, and the adoption of extensive preventive measures and screening measures[7-8].However, when a large number of VCSELs are used in the field[9], the system failure rate can still involve multiple unplanned failures per year when these failures are clustered in large data communication centers with thousands of links.Moreover, in data communication applications, the service life of devices is generally long,usually more than 10 years[10], which demands higher requirements on the reliability of VCSEL devices.Without proper device design, manufacturing and usage, these failure modes lead to high failure rates in oxide VCSELs.For the oxide VCSELs based on GaAs/AlGaAs materials, due to the inherent reasons of device material and structure design, there are potential reliability problems that have received great attention from the industry[11-13].

Therefore, we focus on the most widely used commercial oxide VCSELs[9]made from GaAs/AlGaAs materials in this paper.We expound the common causes of VCSEL failure from the perspectives of device design, manufacturing and external factors, the failure phenomena and mechanisms are summarized and analyzed, and puts forward some improvement suggestions and preventive measures.Through this, it can act as a reference for device R&D and production personnel when they encounter the same or similar situations to quickly and effectively understand their root causes and provide appropriate improvement measures.This will eventually help improve the reliability of the devices.

2 VCSEL structure

An oxide VCSELs structure is composed of a substrate, top and bottom Distributed Bragg Reflector (DBR), quantum wells (also called the active layer), an oxide layer and positive and negative contacts.The light output direction is perpendicular to the wafer surface, and most emit light at 850 nm.A schematic drawing of the oxide VCSEL structure is shown in Fig.1 (Color online).The substrate is usually n-type doped GaAs material.The epi layers are usually grown by Metal-Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy(MBE) on the substrate.The DBRs are multiple pairs of high and low refractive index materials(AlxGa1-xAs materials) grown alternately, where the high-index layer contains the low aluminum content wherexis typically 0.15-0.20.The low-index of the layer has a high aluminum where contentxis typically 0.8-1.0 for 850 nm VCSELs.

Fig.1 Schematic diagram of the oxide VCSEL structure[16]图1 氧化型VCSEL的结构示意图[16]

The quantum wells (usually 3-5 wells) are composed of GaAs/AlGaAs or AlGaAs/InGaAs materials.The oxide layer is AlGaAs with a higher Al concentration or AlAs materials that is located in the p-DBR above the quantum wells, and thickness generally 20-30 nm.It is necessary to etch a mesa structure and then perform selective wet oxidation to form the oxide aperture.This oxide aperture is used to confine current and light.Thus, the threshold current and optical loss can be effectively reduced, so the power conversion efficiency of VCSEL is improved, and the performance of VCSEL is greatly improved[14-15].

3 Common failure modes and analysis

3.1 VCSEL design

3.1.1 Materials system

For any semiconductor laser, the choice of materials system is key, especially the material of the quantum wells used to make the device, and the barrier that makes contact with the quantum well.The widely-used commercial oxide VCSELs are prepared by GaAs/AlGaAs epitaxial materials at present, due to the fact that GaAs and AlGaAs materials have a matched lattice and have a large refractive index difference, so the device has a small DBR thickness to get a high reflectivity and excellent performance, etc.It was found that dislocation is easily formed in GaAs/AlGaAs compound semiconductor materials[17].This may be due to the band gap energy of the material, the bonding force, the size of the crystal atoms, point defects generation energy and migration energy and deep levels, etc.

Table 1 shows a degree of dislocation formation in some different III-V compound semiconductor materials.From this table, it is seen that for almost all of these materials, the larger band gap energy is more likely to form dislocation, such as GaAs and GaP are prone to dislocations, while In-GaAsP materials are not.The mechanism is such that the larger the band gap energy is, the more energy can be provided for the formation of defects.The defects are more conducive for generation and migration.However, according to this theory, InP with a relatively wide bandgap should also be prone to dislocation, but actually it’s not.Bandgap energy alone is not sufficient to explain this behaviour.There are other theories that need further investigation[18-19].

Tab.1 A summary of the easiness of formation of dislocation loops in some III-V compound semiconductors[20]表1 一些III-V族化合物半导体产生位错的难易程度[20]

Another dominant factor is the weakness of the reconstruction energy between GaAs atoms, which causes the activation energy of dislocation motion in GaAs to be low.The recombination is easily broken or affected by impurities, so dislocation defects are easily formed[20].Besides, other dislocation formation factors include the magnitudes of generation energy and migration energy for point defects and deep levels which are related to such defects as dangling bonds and native point defects, and non-radiative recombination rates at the deep levels, etc[20].

A relatively ideal semiconductor laser materials system is one where active materials are prone to dislocation defects but have sufficient compressive stress to prevent dislocation growth[21].As shown in Fig.2, the Dark Line Defect (DLD) was successfully stopped in GaAs-based lasers by inducing compression strain by introducing 5%-7% indium in quantum wells with a suitable relative thickness.The proportion of indium must be within a suitable range.Too little will not prevent DLD growth,such as in the “No pinning” region in the Fig.2.However, introducing too much indium can lead to lattice mismatch and generate DLD, as shown by the solid line above[19].Kirkbyet al.[22]also showed that indium can prevent dislocation generation and migration even in the absence of compressive strain because the large atomic radius of indium can harden the lattice.Therefore, one might consider adding moderate indium into VCSEL quantum wells to introduce compressive strain and lattice hardening to slow down dislocation formation and migration.

Fig.2 The effect of indium content on laser reliability[19]图2 铟含量对激光可靠性的影响[19]

3.1.2 Structure design

(1) Oxide layer

The oxide layer problem is a major source of VCSEL failures and is difficult to avoid.As we know, in oxide VCSELs, the oxide layer (AlxOy) is completed by the vapor oxidation of AlAs or Al-GaAs layer containing a very small amount of Ga by the mesa.After AlAs oxidation forms Al2O3, its volume will shrink by about 20%[23-24], which creates greater stress in the oxide layer, especially at the tip.At the same, AlxOyand DBR semiconductor lattice mismatch has a weak binding force and a thermal mismatch in the Coefficient of Thermal Expansion(CTE) at the interface.Improper control of the oxidation process can easily form delamination or cracks between the two interfaces, which is the main source of dislocation defects.

Herricket al.investigated the origin of dislocations in GaAs-based VCSELs[25].The DLD in the device originates from the oxide tip as shown in Fig.3.According to Transmission Electron Microscopy(TEM) work done by others with DLD networks in the active region of the device[26], the DLD may move down from the tip of the oxide layer to the active region below.The direction of propagation may be driven downward by current and form a DLD network as the line dislocations cross the active region[27].

Fig.3 Trace diagram of DLD in a failed VCSEL viewed from the top and side[25]图3 失效的VCSEL内位错的示意图[25]

The material component, thickness of the oxide layer and oxidation process are the main factors affecting the stress after oxidation.Choquetteet al.[24]studied the influence of oxide materials with different Al contents on laser reliability.They found that AlAs oxide layer material is unstable to the rapid thermal cycle and shows excessive strain at the oxide's end during the wet oxidation process, while AlGaAs is stable after oxidation and can provide reliable oxide aperture for VCSEL, as shown in Fig.4.This is because the oxidation reaction rate of Al-GaAs is lower than that of AlAs, making the oxidation process controllable and isotropic, while the mechanical instability inherent in the mesa containing AlAs oxide layer and the greater volume shrinkage resulting from the conversion of the oxide.

Fig.4 Cross-sectional TEM images of different oxide compositions[24].(a) Al0.98Ga0.02As oxide layer;(b) AlAs oxide layer图4 不同氧化层成分的横截面TEM（XS-TEM）图片[24]。(a) Al0.98Ga0.02As 氧化层；(b) AlAs氧化层

Therefore, in order to increase oxide VCSELs'reliability, it is key to reduce the volume shrinkage and stress of the oxide layer, make the oxidation process more stable and controllable through epitaxial design and through an oxidation process control such as changing the composition of the oxide layer's material, reducing the oxide layer's thickness and the oxidation rate etc[28].

(2) Mesa structure

As mentioned above, when performing the selective wet oxidation process, the oxide VCSEL needs to etch a mesa structure before the oxidation process, and this mesa structure is relatively dangerous for the reliability of VCSELs.Firstly, the manufacturing process of the mesa involves etching,cleaning, oxidation, passivation, etc., and the combination of one or more adverse factors in the manufacturing process leads to subtle mechanical damage near the edge of the mesa, which then becomes the source of defects.Secondly, a DBR is alternately grown from AlGaAs material with low Al content and high Al content.The material with high Al content is usually Al0.92Ga0.08As.Therefore, part of the DBR will be oxidized in the actual oxidation process with about 4 μm in thickness, and DBR has many layers, so the cumulative stress is very high as shown below in Fig.5.Delamination or cracking occurs at high enough stresses, and dislocations move from the edge of the oxide to the active region.

Fig.5 Cross-sectional TEM images of an oxide VCSEL mesa[29]图5 氧化物VCSEL台面边缘的XS-TEM照片[29]

Herrick[29]and Helms[30]found a dislocation network in VCSEL failure analysis as shown in Fig.6.The source of dislocation defects is at the edge of the mesa and gradually propagates to the active region, possibly due to excessive mechanical stress introduced by DBR oxide shrinkage at the edge of the mesa.These defects tend to grow slowly towards the active region in a DBR, but once they reach the active region, they grow rapidly, leading to rapid equipment failure.

Fig.6 TEM images showing a tracing of the dislocation network[30]图6 位错网络轨迹的TEM图像[30]

This problem can be eliminated by inactivating(electro-passivation) the edges of the VCSEL with deep proton implantation to prevent movement of climbing dislocations[31].In addition, Emcore Corporation[30]explored a design without oxides at the mesa edge to eliminate these potential problems,as shown in the original design and experimental design in Fig.7.

Fig.7 Cross-sectional SEM images.(a)Original design.(b)Oxide free design[30]图7 原始图(a)和无氧化物图(b)的截面图(扫描电镜)[30]

3.2 Manufacturing

3.2.1 Substrate and epitaxy

The lattice defects, dislocation defects and impurities of the substrate material will seriously affect the lattice quality of subsequent epitaxy[29].Threading dislocations likely caused the defects.Dislocation will climb from the substrate to the epitaxial layer (by the action of recombination-enhanced dislocation motion) and eventually form a large number of dislocation networks in the active region.Failure occurs when the structure of these dislocation networks reaches a certain level[30].At the same time, the defects in the process of epitaxial growth and the lattice mismatch of heterogeneous materials will affect the quality of the device, and the failure will occur due to the current stress,thermal stress and mechanical stress that cannot be released during use.

Therefore, it is extremely important to minimize the occurrence of any defects in substrate and epitaxial growth[31].It is equally important to minimize the epitaxial stress built into the device, because epitaxial stress amplifies the process.Defects can be reduced by strictly checking substrate defects and controlling the quality process of epitaxial growth.Epitaxial growth quality is very important for VCSEL reliability, so some suggestions for controlling the quality process of epitaxial growth are listed.First, during the development process, epitaxial growth temperature, the doping level and gas flow ratio should be optimized.Then in the process of epitaxial growth, the reaction chamber must be clean and the “sacrificed” epitaxial slice is required for collecting the thickness and doping data.After epitaxial growth, each wafer must go through strict epitaxial defects count check and thickness check to remove defective products.Finally, visual inspection is required to check for epitaxial defects,cracks, etc[29].

3.2.2 Wafer fabrication

VCSELs' wafers have many fabrication processes including etching, cleaning, oxidation, passivation, transport, testing, dissociation, packaging,etc.Each process may cause mechanical damage or microcracks on the chip.Itakura Tet al.[32]observed the failed VCSEL through TEM and found that the dislocation Burgers vector was parallel to the direction [101], as shown in Fig.8.From the branch of the dislocation network, it was speculated that the dislocation developed from the lower-left corner of the inner edge of the oxide aperture to the lower right corner of the oxide aperture.Strain or crystal defects introduced during VCSEL manufacturing are considered to be the origin of dislocations.In addition, metal contamination (gold and copper) during the manufacturing process is fatal to a VCSEL.Metal atoms are equivalent to traps that can capture carriers, causing most carriers to recombine non-radiatively, resulting in chip failure.The equipment,process and raw materials should be strictly controlled.

Fig.8 Plan view TEM of failed VCSEL introduced during manufacturing[32]图8 工艺过程引起失效VCSEL的平面TEM（PV-TEM）图像 [32]

3.3 External factor

The above summary analyzes the causes of failure in the design and manufacturing of VCSEL devices.The main external factors causing device failure are introduced below, including electrostatic discharge (ESD) or electrical overstress (EOS) impact damage, high temperature, high current and high humidity aging and mechanical damage, etc.

3.3.1 ESD/EOS

Emcore company summarized two modes of VCSEL random failure.The first type of failure is an inherent defect in the design and process of VCSELs.In this failure mechanism, dark line defects originate from the edge of the mesa and spreads to the interior of the emitter hole; the second type is caused by ESD or EOS[30].ESD events occur due to a charge imbalance between the device and another object.Such charges can generate pulses of up to 50 μs, but test instruments with switching transients can generate longer pulse widths for stress testing known as EOS.Oxide VCSELs are a kind of electrostatic sensitive device due to the diameter of oxide aperture usually ranging from 7 μm to 12 μm.VCSEL is easily affected by ESD and EOS, which is a major cause of VCSEL failure.

Many companies in the industry, including AOC[8], Emcore[30], Finisar[33-34], Agilent[35-36], Huawei[37]and Honeywell[38]have conducted many special ESD and EOS studies on the failure mode of oxide VCSEL by LIV, reverse IV, electroluminescence, EMMI, TEM and other failure analysis means.Among these failure analysis methods, a better way to judge whether VCSEL suffers ESD damage failure is to test the reverse IV curve.If compared with good devices, VCSELs with leakage increases and “soft knee” appearances are likely to suffer ESD[35].If regardless of the time and money cost, the TEM method including plan-view TEM(PV-TEM) and cross-sectional TEM (XS-TEM) is the most direct and efficient way to distinguish ESD failure characteristics from other types of failure paths[38-39].The overall characteristics and source location of defects can be determined[33].Therefore,once the failure occurs in the VCSEL, the above methods can be used to confirm whether it is caused by ESD and the specific ESD event.Thus, a targeted investigation and improvement can be efficiently performed.

Matheset al.[8,33]summarized the failure characteristics corresponding to different ESD modes to include the Human Body Model (HBM), Machine Model (MM), Charged Device Model (CDM) and EOS, which can be used as a very good base of study for failure analysis by providing more references for similar events in the future and identifying their root causes.Specific PV-TEM and XSTEM results and the characteristics of failure are summarized as follows.

(1) Reverse HBM model

The HBM mode simulates the electrostatic release process of human body contact devices.HBM is the most common and disruptive event for VCSELs.It can be subdivided into forward voltage and reverse voltage shock modes.VCSEL has a lower reverse HBM damage threshold due to power dissipation.The failure characteristics of VCSELs under forward and reverse HBM ESD models were studied in Refs.[40-41].As shown below in Fig.9,the dislocations occur in the interior near the edge of the oxide aperture, and the damage size is approximately a few millimeters in the reverse HBM model.XS-TEM shows that the quantum well melts locally and tangles in the vertical direction, especially in layers with high gallium content.

Fig.9 TEM micrographs of a device subjected to a reverse HBM event[33].(a) Plan-view; (b) cross-section图9 反向HBM模式损伤的TEM图片[33]。(a) 平面图；(b) 截面图

(2) Forward HBM model

In this mode, dislocations occur at the edge of the oxide aperture where the size is on the order of several hundred nanometers with dislocation density and permanent thermal damage lower than those in the reverse bias HBM mode, as shown in Fig.10.

Fig.10 TEM micrographs of a device subjected to a forward HBM event[33].(a) Plan-view; (b) cross-section图10 正向HBM模式损伤的TEM图片[33]。 (a) 平面图；(b) 截面图

(3) MM model

The MM mode simulates the electrostatic release process of device and equipment contact.As shown in Fig.11, in the MM mode, dislocations are distributed on both sides of the edge of the oxide aperture and the size is several hundred nanometers.The dislocation extends from above the oxide layer to below the quantum well layer, and there is a higher dislocation density in the high gallium layer.

Fig.11 TEM micrographs of a device subjected to an MM event[33].(a) Plan-view; (b) cross-section图11 MM模式损伤的TEM图片[33]。(a) 平面图；(b) 截面图

(4) CDM model

The CDM model simulates the accumulation of charge on the device and subsequent discharge when the device comes into contact with other objects.This mode has the shortest duration and the highest pulse intensity of all ESD models.In Fig.12, TEM results show that there is a circular distribution of damage in the oxide layer,which may be related to the shape of the electrode.Dielectric breakdown occurs throughout the oxide layer, sometimes extending to the quantum well region.

Fig.12 TEM micrographs of a device subjected to a CDM event[33].(a) Plan-view; (b) cross-section图12 CDM模式损伤的TEM图片[33]。(a) 平面图；(b) 截面图

(5) EOS model

EOS usually refers to damage caused by a high current over a long period of time.We used a 45 mA DC current (far beyond the normal operating current of the device) to power up the VCSEL for 960 s.TEM results show that the defects occur in a wide area of the oxide aperture, and the dislocation extends from the top of the oxide layer to the bottom of the quantum well layer as shown in Fig.13.

Fig.13 TEM micrographs of a device subjected to an EOS event.(a) Plan-view; (b) cross-section图13 EOS模式损伤的TEM图片。(a) 平面图；(b) 截面图

Ref.[42] and our own work have also verified similar experimental results as mentioned above.It can be seen that TEM results of different ESD models are significantly different, which will help to judge the causes of problems and formulate corresponding measures in a more detailed manner.The mechanism of different results is that the oxide layer area of VCSEL is equivalent to a capacitor, and different ESD modes have different impact times,frequencies and intensities, resulting in different defect sizes and different defect positions relative to the oxide layers.

ESD is harmful to components and devices,leading to their failure and interruption of services.It is necessary to prevent ESD in the following four ways.

1.VCSEL design: The oxide aperture is the key parameter that determines the ESD's grade.With the intention of satisfying performance characteristics, increasing the diameter and uniformity of the oxide aperture as much as possible is the way to improve the ESD tolerance level of the device[36,43].

2.Process control: In VCSEL device manufacturing, modules and even equipment manufacturing processes should pay attention to ESD protection and control in every aspect including equipment, operation, process, personnel, environment, etc.Fig.14 below shows the preventive measures taken to prevent ESD generation in the VCSEL manufacturing workshop.

Fig.14 Preventive measures taken to prevent electrostatic discharge in VCSEL workshop[30]图14 VCSEL 生产车间为防止静电放电所采取的预防措施[30]

3.Screening: Reverse IV testing and Burn-In accelerated aging can screen out components damaged during VCSEL manufacturing and eliminate early failure samples[36,44].

4.Packaging circuit protection: VCSEL chips are packaged into TO devices or modules, and zener diodes[45]or integrated circuit protection circuits[35]are added to prevent ESD damage to VCSELs.The zener diode protection circuit is shown in Fig.15, where they are connected in inverse bias parallel.The current-shunting effect of Zener diodeis used to protect VCSEL from ESD damage.

Fig.15 VCSEL and Zener Diode package diagram图15 VCSEL和齐纳二极管封装图（Zener Diode）

3.3.2 High temperature, current and stress

As we know, high temperature and high current are two main factors affecting a semiconductor laser's life.Defects in the device will generate and expand under high temperatures and high currents until failure.Stress can have the same effect and accelerate aging.Stress comes from issues such as semiconductor lattice mismatching, device processing, and possibly from other nearby dislocations.These external driving stresses provide the energy for defect generation and defect movement,which can accelerate device failure[46].

It was found that temperature, current and stress have the following rules for the generation of defects in semiconductor lasers[46-49]:

1.Thermal stress is the main factor causing dislocation, and dislocation will move and proliferate under stress.Dislocation slip is an intense thermal activation process in GaAs and is almost frozen at temperatures below 300 K.

2.When the current density of a VCSEL reaches a certain value, DLD defects begin to occur in the laser.DLD growth is strongly dependent on driving conditions, so a slight reduction in current will significantly slow down DLD growth.In the absence of current, DLD defects are not observed even at high temperatures or stresses.

3.The dependence of degradation rate on stress and current increases significantly when both stress and current are applied at the same time.Therefore,both injection and stress are necessary for rapid defect growth.

Maeda K[50]and Yonenaga[51]et al.studied the relationship between defect movement velocity and temperature, current, stress and material activation energy in semiconductor devices.The influence of temperature is in line with the Arrhenius equation,and the influence of current and stress on dislocation is a power series relationship, expressed in Eq.(1).

whereτis stress,Iis current,Tis the temperature,Eais the activation energy,kBis the Boltzmann constant,AandBare scaling parameters,mandnare power exponents.

The main measures are to avoid the device working under high current, temperature and stress.One is to increase the heat dissipation capacity of the VCSEL package, and use it with proper process and a high thermal conductivity of submount, etc.An other measure is to specify the maximum current and maximum temperature under normal use conditions.

3.3.3 Humidity

Humidity can also accelerate device aging.Dafincaet al.[52]gave a formula for the influence of temperature, current and relative humidity on device median time to failure.The current and temperature are consistent with the above Eq.(1) and the effect of humidity on median time to failure is exponential, as shown in Eq.(2).

whereRHis relative humidity,ARHis humidity factor, andCis the scaling parameter.

At present, due to the cost and application requirements, VCSELs used in data communication generally adopt non-hermetic packaging.Oxide VCSELs are known to be vulnerable to atmospheric humidity which is a big challenge[53].We need to know the failure mechanisms and to protect against water vapor.Xieet al.[54-56]summarized three main failure modes of oxide VCSELs in a high humidity environment: dislocation growth, semiconductor cracks and optical window surface degradation.The specific failure modes and characteristics are summarized as follows.

(1) Dislocation

Dislocation in oxide VCSELs is the most common failure mode under high temperature and high humidity conditions.As shown in Fig.16, a mass of dislocation networks was observed in the quantum wells region of the samples that failed under 85/85 testing with bias current.The cause of the dislocation is related to the oxide layer, because this failure mode is not observed in the proton injection VCSEL.In addition, this failure mode must be driven by bias current as the same mode does not appear only in high temperature and high humidity conditions.Water vapor corrodes in the oxide layer driven by bias current, resulting in As depletion and excess Ga, which becomes point defects in the form of gaps.When the point defects accumulate to a certain extent to form dislocations, they eventually lead to failure.

Fig.16 Dislocation of oxide VCSEL under humidity corrosion[54-56].(a) PV-TEM; (b)XS-TEM图16 氧化型VCSEL湿热腐蚀下的位错TEM图片[54-56]。(a)PV-TEM；(b)XS-TEM

(2) Semiconductor crack

This failure mode is also unique to the oxide VCSEL and is not found in implanted VCSELs.The same wafer has no cracks in only high-temperature reliability tests, but the crack rate is very high in the high-temperature and high-humidity test.As shown in Fig.17, semiconductor cracks begin at the oxide tip.Due to moisture accumulation in the oxide layer and the thermal gradient of bias current in high-temperature and high-humidity tests, cracks appear and expand in the oxide tip where stress is high.Due to changes in the manufacturing process, devices with high built-in stress are prone to this kind of cracking.

Fig.17 Semiconductor crack of oxide VCSELs under humidity corrosion[54-56].(a) Case1; (b) Case2图17 氧化型VCSEL湿热腐蚀下的半导体裂纹[54-56]。（a）情形1；（b）情形2

(3) Aperture surface degradation

The degradation of the aperture surface during high temperature and humidity may be due to a reaction between surface GaAs, moisture and contaminants (if any), as shown in Fig.18.Atmospheric cleanliness can cause this failure mode, which is accelerated by bias currents.This failure mode is not unique to oxide VCSELs.

Fig.18 SEM of aperture surface degradation of oxide VCSEL after humidity corrosion[54-56]图18 氧化型VCSEL湿热腐蚀下的光窗表面退化SEM图片[54-56]

Dafinca[52]and Herrick[25]studied the mechanism of moisture corrosion leading to VCSEL failure,as shown in Fig.19.Moisture corrosion occurs near the oxide tip, leading to cracking.Cracking near the oxide tip causes dislocations to move down to the active region, which usually takes years to grow.Once it infiltrates the active area, a DLD network grows rapidly in the active region and the device fails completely within minutes.

Three protection measures are proposed when a VCSEL works in a non-hermetic environment to protect against the failure modes and mechanisms.

Fig.19 Schematic diagram of VCSEL corrosion failure mechanism[52]图19 VCSEL腐蚀失效机制示意图[52]

Firstly, chips' “extrinsic” design is addressed.A protective passivation layer (coat) should be deposited on the outside of the chip to prevent water vapor from eroding into the inside of the device through deposition methods including Plasma Enhanced Chemical Vapor Deposition (PECVD) and Atomic Layer Deposition (ALD).The specific materials of the protective film may be Al2O3, SiO2,AlN, etc[57].At the same time, the thickness of the protective film should be well controlled: too thin cannot properly protect the chip and too thick will cause too much stress and affect its reliability.

Secondly, chips' “intrinsic” design is addressed.As mentioned above, the chip should have a strong oxide layer design.By controlling the thickness of the oxide layer and the oxidation process conditions,reduces the internal stress of the chip, especially the shrinkage stress after oxidation, increases the atomic bonding density of the oxide layer, and slows down the water vapor reaction inside the device.

Thirdly, the chip must be externally protected to create the effect of “hermetic” packaging.As shown in Fig.20, the chip can be coated with an appropriate thickness of the epoxy resin to prevent water corrosion[25,58-59].

Fig.20 Coating epoxy resin to protect the VCSEL[25]图20 使用环氧树脂对VCSEL进行保护[25]

3.3.4 Mechanical damage

Damage caused by external stress, such as cracks and scratches, can become the source of dislocation formation[32,60].For oxide VCSEL, the mechanical damage propagating inward from the edge of the mesa is always a risk[61].When mechanical damage is introduced from outside, dislocation defects will continue to grow from the source of the damage point in the subsequent use process, and finally cause failure[11].Fig.21 shows an example of how a scratch can cause DLD.The two photos on the left show the SEM images of the scratches.The central image shows the electroluminescence (EL)of the received failed VCSEL.The image on the right shows the DLD moving from the bottom left to the top right.After a few minutes at 10 mA, the DLD continues to grow to the right[11].

Fig.21 Example of DLD caused by scratch[11]图21 刮伤引起DLD的示例[11]

Typically, a strict 100% visual inspection is carried out to remove damaged parts during the process, or the chip is designed to prevent mechanical damage from spreading to the active region by wetetching grooves of appropriate width, or electrically passivating the mesa edge material.

3.4 Some case study

In order to serve readers with a more comprehensive failure analysis, in addition to the VCSEL production design company and the research achievements of academic literature, we also collected a set of failure mode summary results.Three typical failures in accelerated aging validation are shown below for supplementary reference.The failure causes include epitaxial defects, oxidation anomalies, mesa oxidation stress, ESD and DLD.

(1) Case 1

Fig.22 shows TEM images of samples that failed during high temperature and high current testing.It can be seen that there are two main failure characteristics: abnormal oxidation at the edge of the oxide layer and epitaxial dark spot defects in the active region.The causes of these two problems are related to the quality of the oxidation process and epitaxial growth, respectively.

Fig.22 TEM images of Case 1.(a)Overall PV-TEM.(b)Partial enlargement in the (a) dotted box.(c)XSTEM in the (b) dotted box图22 案例1失效样品的TEM图片。（a）整体PV-TEM；（b）局部放大图；（c）XS-TEM图片

(2) Case 2

Fig.23 shows TEM results of VCSEL failure after aging for 500 h at a high temperature and high current.Fig.23(a) shows a DLD network diagram.The origin of dislocation is the oxidized mesa edge which gradually moves to the active region as it ages.As shown in Fig.23(c), cross-sectional TEM results, the thickness of the oxide layer is about 100 nm at the edge of the mesa, far beyond the normal thickness of the oxidation tip by about 20 nm.This is the root cause of failure due to the oxide layer being too thick at the mesa's edge.

Fig.23 TEM image of Case 2.(a)Overall PV-TEM.(b)Partial enlargement in the (a)dotted box.(c)XSTEM图23 案例2失效样品的TEM图片。（a）整体PV-TEM；（b）局部放大图；（c）XS-TEM

(3) Case 3

The TEM results of Fig.24 show failure samples in high temperature and high humidity(85/85) tests.The failure mode is that there are many defects at the edge of oxide aperture, which are especially severe at the oxidation corner area where stress is largest.At the same time, many DLD networks are generated with oxide aperture defects as the starting point, which is consistent with Krueger's research results.ESD failure characteristics are usually accompanied by DLD dislocations.If the device continues to work or age after ESD damage, DLD will diffuse and develop at the damaged location[36].

Fig.24 PV-TEM images of Case 3图24 案例3失效样品的PV-TEM图片

4 Conclusion

The reliability of the oxide VCSEL is closely related to the materials system, device design, substrate and epitaxial, process quality and external factors.Among these factors, the materials system determines the degree of defect generation, VCSELs made of GaAs/AlGaAs materials are also vulnerable to dislocations.The oxide layer and etched mesa structure introduce an inherent defect source,and most of the failure modes are associated with oxidation stress.Substrate, epitaxy and the manufacturing process determine the density of defects in the device.External factors introduce the source of defects and also can provide the driving force for the generation and multiplication of defects.Among them, VCSELs are susceptible to ESD stress and in non-hermetic applications, humidity and heat corrosion are also major factors of VCSEL failure.

This paper summarizes and analyzes the common failure modes and causes in oxide VCSELs,and puts forward corresponding improvement suggestions and preventive measures.It can provide a good reference for VCSEL practitioners to help identify the source of the problems, dig out the root causes and implement appropriate measures for improvement.In such a way, the high reliability and low failure rate of the VCSEL devices can be improved gradually in field applications.It has important practical engineering significance.More comprehensive and accurate failure causes and mechanism models need further study in the future.

——中文对照版——

1 引 言

垂直腔面发射激光器（Vertical Cavity Surface Emitting Laser，VCSEL）拥有阈值低、功耗低、速率高、易于集成和成本低等优点，是短距离数据通信的核心光源，其中绝大多数采用GaAs体系材料，在850 nm波长下发光，主要用于数据通信和光学跟踪应用[1-4]。

可靠性作为半导体激光器能够长期使用的一个关键的指标，对应用非常重要，是器件开发设计和应用的核心问题[5-6]。随着设计能力和工艺水平的提升，以及采取了广泛的预防措施和筛选措施，目前半导体激光器的现场故障率达到了10 ppm /年[7-8]，但是如果没有进行适当的器件设计、制造和使用，将导致器件具有较高的故障率。而且VCSEL每年发货数量庞大[9]，即使低的失效率也会有绝对数量的不良品，当这些故障聚集在拥有数千条链路的大型数据通信中心时，系统的故障率仍可能涉及每年多次计划外故障，同时在数据通信应用中对器件的使用寿命一般比较长，通常在10年以上[10]，这对VCSEL器件的可靠性提出了较高的要求。对于以GaAs材料为基础的氧化限制型VCSEL，由于器件材料和结构设计的固有原因，会有潜在的可靠性问题，受到工业界的极大关注[11-13]。

因此，本文以目前商业化应用最广的氧化限制型850 nm VCSEL为对象[9]，从器件设计、加工制造和外界因素等三个方面详细阐述导致VCSEL失效的常见原因，总结了失效的模式及失效机理，并给出一些预防措施和改善建议，通过研究VCSEL的失效模式及机理，可以为VCSEL从业人员提前预防失效的发生，当问题发生时也可以作为一个参考，从而更加快速有效地了解问题产生的根本原因，并进行合理的改进，以提升器件的可靠性。

2 VCSEL 结构

氧化型VCSEL 的结构是由衬底（substrate）、上下布拉格反射镜(DBR)、量子阱有源区（active layer）、氧化限制层（oxide layer）、上下电极（contact）组成，光输出方向垂直于晶圆表面，激射波长为850 nm。氧化型VCSEL的器件结构示意图如图1所示。衬底一般是n型掺杂GaAs材料，DBR是由两种不同折射率材料（不同Al含量的AlGaAs）交替生长而成，有源区由GaAs/AlGaAs或AlGaAs/InGaAs多量子阱组成。氧化限制层是通过对含高Al成分的AlGaAs或者AlAs材料进行选择性湿法氧化得到Al2O3结构，氧化层厚度一般为20～30 nm，氧化后的孔径一般为7～12 μm，能够对电流和光场起到有效的限制作用，从而可以有效降低阈值电流和光损耗，提高VCSEL的功率转换效率，大大提高了VCSEL的性能[14-15]。

3 常见失效原因及分析

3.1 VCSEL 设计

3.1.1 材料体系

由于GaAs和AlGaAs材料的晶格匹配，能带范围决定了可以在850 nm范围内发光，同时两种材料具有较大的折射率差，器件可以在较小的DBR厚度下获得较高的反射率和优异的性能，所以目前商业化广泛应用的氧化型VCSEL由GaAs/AlGaAs材料制备而成。但是研究发现GaAs/Al-GaAs化合物半导体材料容易形成位错[17]，这可能是由于材料的能带间隙、晶体原子结合力、原子尺寸大小、缺陷能级及点缺陷的形成能和迁移能等因素导致的。表1为一些Ⅲ-Ⅴ族化合物半导体材料形成位错的难易程度。可以看出，具有较大能带间隙能的材料，如GaAs和GaP容易形成位错，而带隙能较小的InGaAsP材料则不会，这是由于能带间隙能越大，可以提供给缺陷形成的能量就越大，因此缺陷越容易产生和运动。然而，带隙相对较宽的InP却不容易产生位错，这说明仅从带隙能角度并不能充分解释，还有其他机理有待进一步研究[18-19]。

另外，GaAs原子间的重建能量相对较弱，GaAs中位错运动的活化能较低，而且重组很容易被杂质破碎或受杂质影响，因此容易形成位错缺陷[20]。此外，位错形成的影响因素还包括与悬空键和原生点缺陷等缺陷相关的点缺陷和深能级的生成能和迁移能的大小，以及深能级的非辐射复合率等。

对于半导体激光器的一种较为理想的材料体系是有源区材料虽然容易产生位错缺陷，如本文研究的GaAs基VCSEL，但是有源区材料具有足够的压缩应力可以阻止位错生长[21]。如图2所示，在适当的量子阱厚度下，通过在量子阱中引入5%～7%的铟，诱导压缩应变，成功地在GaAs基激光器中阻止了位错（Dark Line Defect，DLD）产生。铟元素的比例有个合适的范围，太少起不到阻止DLD生长的作用，如图2虚线左侧部分[19]。然而，引入过多的铟会导致晶格失配而产生DLD，如图2中实线右上部分。Kirkby[22]和其他人也指出，即便在没有压缩应变的情况下，铟也能阻止攀爬和下滑。这是因为In有较大的原子半径，可以使晶格硬化，阻止位错的产生和迁移。因此，可以考虑在VCSEL有源区材料内增加适量的铟以引入压缩应变和晶格硬化来减缓位错的形成。

3.1.2 结构设计

(1) 氧化层

氧化问题是VCSEL失效的主要原因，而且是一个很难避免的难题。众所周知，氧化型VCSEL中，由于氧化层（AlxOy）是由AlAs或含有极少量Ga的AlGaAs层经过台面水汽氧化得到的，AlAs氧化形成AlxOy时体积会有约20%的收缩[23-24]，这样就会在氧化层，尤其尖端，形成较大的应力，同时由于氧化后形成的氧化铝和DBR半导体晶格不匹配，结合力弱，以及热膨胀系数（CTE）不匹配等，如果氧化工艺控制不当很容易在两者界面之间形成分层或者裂纹[23]，成为位错缺陷形成的主要源头。

Herrick等人研究了GaAs基 VCSEL的位错的起源[25]，如图3所示，认为器件内的线DLD起源于氧化物尖端。基于其他人对器件有源区内有DLD网络的透射电子显微镜（TEM）工作可知[26]，认为线位错可能从氧化层尖端向下移动到下面的有源区，传播方向可能是受到电流向下的驱动[27]，并在线位错穿过有源区时形成DLD网络。

氧化层的材料组分、厚度和氧化工艺等是影响氧化后应力的主要因素。Choquette等人[24]对不同Al含量氧化层材料对可靠性的影响进行了研究，在湿法氧化过程中，AlAs氧化层材料对快速热循环不稳定，在氧化端表现出过度的应变，而AlGaAs材料氧化后则是稳固的，可以为VCSEL提供可靠的氧化孔，如图4所示。这是因为AlGaAs的氧化反应速率比AlAs的低，故其氧化过程可控、各向同性，而包含AlAs氧化层的台面中存在固有的机械不稳定性以及转换氧化物后更大的体积收缩。因此，可以通过改变氧化层材料成分、降低氧化速率和减少氧化层厚度等方式来降低氧化层的应力和减小体积收缩，增加VCSEL可靠性[28]。

(2) 台面(mesa)结构

氧化型VCSEL在选择性湿法氧化工艺时，需要蚀刻出一个台面柱状（mesa）结构，然后再进行氧化工艺，而该结构设计对器件的可靠性来说是比较危险的。一是器件台面制作过程中涉及蚀刻、清洗、氧化和钝化等工序，加工过程中一种或者多种不利因素的组合导致台面边缘附近细微的机械损伤，而后成为缺陷的源头；二是DBR是由低Al含量和高Al含量的AlGaAs材料交替生长而成的，高Al含量的材料通常是Al0.92Ga0.08As，因此在实际氧化过程中也会有部分被氧化，一般为4 μm左右，而且DBR有很多层，所以累积应力非常高，如图5所示。当应力足够高而引起分层或者裂纹时，位错会从氧化物的边缘向有源区移动。

Herrick[29]和Helms[30]对失效的VCSEL分析发现这是由于DBR氧化物收缩而引入过度的机械应力导致的失效，如图6所示的位错网络，图中TEM图像显示位错可疑的起点在靠近台面氧化物的边缘，并逐渐向发光区传播。这些缺陷在DBR中向有源区域缓慢增长，一旦它们到达有源区域，就会迅速增长，从而导致设备快速失效。

对于前面所讨论的台面侧面会有部分DBR氧化引入应力或分层的问题，可以通过深质子植入方法使VCSEL的边缘失去活性（电钝化）来消除，以防止攀爬位错的运动[31]。另外，Helms等人[30]探索一种在台面边缘没有氧化物的设计，以消除这些潜在的问题，原始设计和实验设计如图7所示。

3.2 加工制造

3.2.1 衬底和外延

衬底材料自身的晶格缺陷、位错缺陷和杂质会严重影响后续外延的晶格质量[29]，位错会从衬底层向外延层中攀爬（通过非辐射复合增强缺陷攀移运动的作用），最终在有源区中形成大量的位错网络结构。当这些位错网络结构达到一定程度的时候，就会产生失效[30]。

同时，外延生长过程中的缺陷以及异质材料晶格失配问题都会影响器件的质量，在使用过程中出现无法释放的电流应力、热应力和机械应力而产生失效。

因此，衬底和外延生长中尽量减少任何缺陷的发生是极其重要的[31]。同样重要的是尽量减少器件内建的外延应力，因为外延应力会放大这一过程。通过严格检查衬底缺陷和控制外延生长的质量，可以减少缺陷的产生。对于外延生长质量的控制，首先，在开发过程中应优化外延生长温度、掺杂水平和气体流量比等；然后在外延生长过程中，反应室必须是干净的，需要用陪片来收集其余外延片的厚度和掺杂等数据；外延生长完成后，每片晶片都必须经过严格的外延缺陷计数检查和厚度检查，剔除不良产品。最后，需要目视检查外延缺陷、裂纹等[29]。

3.2.2 工艺环节

由于VCSEL的制作工艺流程较多，涉及蚀刻、清洗、氧化、钝化、转运、测试、解离、封装等工序，每个工序都可能会对芯片造成机械损伤，微裂纹等。Itakura等人[32]通过TEM观察失效的VCSEL发现位错柏式矢量平行于[101]方向，如图8所示，从位错网络分支来看，推测位错是从氧化孔内缘左下角附近开始向氧化孔右下角发展的。在VCSEL制造过程中引入的应变或晶体缺陷被认为是位错的起源。

另外，工艺制造环节金属（金、铜）污染对于VCSEL是致命的，金属原子在半导体激光器中相当于陷阱，会捕获载流子，从而导致大部分载流子以非辐射方式复合，最终导致芯片失效。因此，要对使用的设备、工艺过程和原材料进行严格管控。

3.3 外部因素

上述总结分析了氧化型VCSEL器件本身在设计和制作中产生失效的原因，下面从应用过程的角度分析一些主要的外在因素引起失效的机理，包括静电放电（ESD）或者电过应力（EOS）冲击损伤，高温、高电流及高湿的老化和机械损伤等。

3.3.1 ESD/EOS

Emcore公司对VCSEL的随机失效总结出两种模式，第一类失效在VCSEL的设计和工艺中的固有缺陷，在这种破坏机制中，暗线缺陷起源于台面的边缘，并向发射孔的内部传播。第二类是由于ESD或EOS引起的[30]。ESD事件是由于器件和另一个物体之间的电荷不平衡而发生的，这种电荷产生的脉冲时间较短，具有开关瞬变的测试仪器可以产生更长的脉冲宽度电流冲击，这种称为EOS。VCSEL是一种静电敏感器件，氧化型VCSEL的氧化孔直径一般为7 μm至12 μm，使得VCSEL容易受到ESD和EOS的影响，是VCSEL失效的一大主要原因。

很多行业内的公司，包括AOC[8]，Emcore[30]，Finisar[33-34]， Agilent[35-36]， Huawei[37]和Honeywell[38]等，对VCSEL ESD的失效模式进行了许多专项的研究。对器件人为引入人体模式（HBM）、机器模式（MM）、组件充电模式（CDM）等不同ESD模式和EOS冲击，然后通过测试LIV、反向IV、电致发光（EL）、发光显微镜（EMMI）和TEM等进行表征，建立不同ESD模式和失效特征的联系，从而建立一个ESD失效案例库以在后续发生失效时进行比照参考。而对于判断VCSEL是否遭受到ESD损伤失效比较好的分析方式，一是通过测试反向IV曲线，如果与好的器件相比漏电增加和出现“soft knee”的特征，很可能是遭受到了ESD[33]，但是这并不能直接确定ESD就是失效的根本原因。然而，如果不考虑时间和金钱成本，通过TEM方法（包括PV-TEM和XS-TEM）是最直接有效的方式，是区分ESD故障与其他类型故障路径的最佳方法之一[38-39]，可以判断缺陷的整体特征和发生源头位置等信息[36]。因此，一旦VCSEL出现失效，可以通过上述方法确认是否是ESD导致，以及具体是哪种ESD模式，从而有针对性地进行排查和改善。Mathes等人[8,33]总结出了不同ESD模式对应的PV-TEM和XS-TEM特征，具体失效TEM结果和特征总结如下。

(1) 反向HBM模式

HBM模式模拟人体接触器件的静电释放过程，对于VCSEL来说，HBM是最常见和最具破坏性的模式。这里分为正向电压和反向电压冲击模式，由于功率耗散的原因，VCSEL具有较低的反向HBM损伤阈值。其中，文献[40-41]具体研究了氧化物VCSEL在正向和反向HBM ESD模型下的失效特征。图9的TEM结果显示，反向HBM模式下位错发生在靠近氧化孔径边缘的内部，损伤尺寸大小为毫米量级。XS-TEM显示量子阱局部会融化，并发生在垂直方向。横向位错会缠结，特别是在含镓量高的层中。

(2) 正向HBM模式

如图10所示，这种模式下位错发生在氧化孔径边缘，大小在数百纳米量级。位错密度和永久性热损伤比反向偏置HBM模式低。

(3) MM模式

MM模式模拟设备和器件接触的静电释放过程。如图11所示，这种模式冲击下位错分布在氧化物孔边缘的两侧，大小为数百纳米量级。位错从氧化层上方延伸到量子阱层下方，在高含镓层中有更高的位错密度。

(4) CDM模式

CDM模式是模拟操作不当时，器件上积累电荷，随后当器件和其他物体接触时放电的过程。这种模式的持续时间最短，脉冲强度最高。图12的TEM结果显示在氧化层会形成圆环形分布的损伤，这可能和电极的形状有关。整个氧化层会出现介电击穿现象，有时延伸到QW层。

(5) EOS模式

EOS通常是指长时间大电流的损伤，本文采用45 mA直流电流（远超过器件正常工作电流）持续960 s对VCSEL进行加电模拟，图13的TEM结果显示缺陷发生在整个氧化层较广的区域，氧化层和DBR半导体层在高电流应力下出现分层现象。

对于以上几种模式，文献[42]和本课题组都得出了相似的实验结果。可以看出，损伤基本上分布在氧化孔周围，不同ESD模式的TEM结果会有明显的不同，这将有助于更加准确地判断问题产生原因并制定相应措施。产生不同结果的原因可认为是VCSEL的氧化层区域等效为一个阻抗，而不同ESD模式的冲击时间、频率和强度不同从而导致损伤点相对于氧化层的位置以及缺陷大小具有不同的特征。

ESD对器件和设备的危害比较大，会显著降低器件的使用寿命或者直接导致器件和设备失效而中断业务，因此，对ESD的防护是有必要的，可以通过如下方式减少VCSEL在应用过程中的失效：

（1）器件设计：VCSEL中的氧化孔径是决定ESD等级的关键参数，在满足性能特性的情况下，尽可能增加氧化孔径的直径和均匀度以提高器件耐受ESD等级[36,43]；

（2）过程管控：在VCSEL器件制造，包括模块到设备制造过程中的每个环节（设备、操作、过程、人员、环境等）注重ESD的防护和管控，图14显示了VCSEL生产制造车间内为了防止静电产生所采用的预防措施。

（3）筛选不良：反向IV测试和burn in能够筛选出在VCSEL制造过程中损坏的器件，剔除早期失效样品[36,44]，在器件正式投入使用前需要经过上述方法进行100%筛选。

（4）封装电路保护：将VCSEL芯片封装到TO器件或者模块中，增加齐纳二极管[45]或者IC保护电路等都可以防止ESD损伤VCSEL[35]。图15是VCSEL和齐纳二极管（Zener Diode）封装图，两者电极反向并联，利用齐纳二极管的分流作用保护VCSEL免受ESD损伤。

3.3.2 温度/电流/应力

众所周知，激光器在高温和高电流驱动下会加速老化，温度和电流是影响寿命的两个主要因素，器件内的缺陷会在高温高电流“催化”下产生、扩展直至失效。应力（例如来自半导体晶格常数失配、器件加工的应力，也可能是来自附近其他位错的应力）也会有同样的效果。这些外在的驱动应力为缺陷产生以及缺陷移动提供了能量，会加速器件失效[46]。

研究发现[46-49]，温度、电流和应力对半导体激光器内缺陷的产生有如下规律：

（1）热应力是位错产生的主要因素，在应力的作用下，位错会发生运动和增殖。位错滑移在砷化镓中是一个强烈的热激活过程，在300 K温度以下几乎冻结。

（2）在VCSEL器件工作过程中，当电流密度达到一定值时，在激光器中就开始产生 DLD 缺陷。DLD的增长强烈地依赖于驱动条件，电流的略微降低会显著减缓DLD的增长。在没有电流的情况下，即使加的温度或者应力很高也不会观察到DLD缺陷。

（3）在同时施加应力和电流的情况下，退化率对应力和电流的依赖性显著增加。因此，注入(即非辐射复合能源)和应力对缺陷的快速生长都是必要的。

Maeda K[50]和Yonenaga[51]等人研究半导体器件内缺陷的移动速度和温度、电流、应力以及材料的激活能等的关系，温度的影响关系符合Arrhenius方程，电流和应力对位错的影响是幂级数的关系，表达公式如下。

式中，τ为应力，I为电流，T为温度，Ea为激活能，kB为玻尔兹曼常数，m，n为幂指数，A和B为比例参数。

主要措施是避免器件在大电流、高温高应力下工作，一是增加VCSEL的封装散热能力，二是规定好正常使用条件下的最大电流和最高温度。

3.3.3 湿度

湿度也可加速器件老化，Dafinca[52]等人给出温度、电流和相对湿度对器件寿命（Median time to failure）的影响公式，其中电流和温度的影响关系同公式(1)，湿度对寿命的影响符合指数关系，具体如表达式(2)所示：

其中，f(I)、f(T)、f(RH)分别为电流、温度和相对湿度有关的函数，C为和电流有关的系数，Ea为激活能，RH为相对湿度，ARH为湿度因子。

目前，从成本和应用等角度考虑在数据通信中使用的VCSEL一般采用非气密封装，但是氧化型VCSEL很容易受到湿气的影响[53]。因此，器件需要有水汽防护能力，这对VCSEL是一个比较大的挑战。Xie等人[54-56]总结出3种主要氧化型VCSEL在高湿环境下的失效模式：位错增长，半导体裂纹和光窗表面退化，具体失效模式和特征总结如下。

(1) 位错

在氧化型VCSEL中，位错是高温高湿条件下最为常见的一种失效模式，如图16所示，在高温高湿加偏置电流条件下，可观察到失效样品在量子阱区域有大量的位错网络。区别于ESD类型故障，此种失效特征在氧化层尖端没有任何损伤，仅在量子阱区域存在位错。这为区分这两种类型提供了一个重要的方法。同时，正向偏置电阻和反向漏电的增加是这种失效模式的额外特征[35]。

位错的发生和氧化层有关系，因为在质子注入VCSEL中没有观察到这种失效模式。而且出现此种失效模式必须要有偏置电流的驱动，只在高温高湿条件下没有出现相同模式的失效。在偏置电流驱动下，水汽在氧化层中发生腐蚀反应，导致As耗尽而留下过量的Ga，过量的Ga以间隙的形式成为点缺陷，点缺陷积累到一定程度形成位错，最终导致失效。

(2) 半导体裂纹

这种失效模式也是氧化型VCSEL独有的，质子注入型VCSEL没有。相同晶片在没有湿度的高温可靠性实验中没有出现裂纹，在高温高湿试验中裂纹发生率却很高，如图17所示。裂纹起源于氧化尖端，这是由于在高温高湿试验过程中，氧化层中的水分积累以及偏置电流存在热梯度，在应力较大的氧化尖端出现裂纹并扩展。由于制造工艺的变化，具有较高内置应力的器件容易发生这种开裂。

(3) 光窗表面退化

高温高湿期间，光窗表面退化可能是由于表面砷化镓、水分和污染物(如果有的话)之间的反应，如图18所示。大气清洁度可能导致这种故障模式，偏置电流下会加速这种故障模式，这种失效模式不是氧化物VCSEL所独有的。

Dafinca[52]和Herrick[25]研究了湿气腐蚀导致VCSEL失效的机理，如图19所示，湿气腐蚀在氧化尖端附近发生，从而导致开裂，氧化尖端附近的开裂导致位错向下移动到活性区域，这通常需要生长数年的时间。一旦它渗透到有源区域，有源区域的DLD网络就会迅速增长，并在几分钟内使器件完全失效。

从失效模式和机理可以看出，VCSEL芯片工作在非气密环境下，需要三方面的防护措施。第一，芯片“外在”设计，要在芯片外面沉积一层保护钝化层（“coat”），防止水汽进入到器件的内部。沉积方法有等离子体化学气相沉积（PECVD）、原子沉积（AlD），保护膜的具体材料可能是Al2O3、SiO2、AlN等[57]。同时，保护膜的厚度也要控制好，太薄起不到保护作用，太厚会造成应力过大，影响可靠性。第二，如上所述芯片“内在”的氧化层强壮设计，通过氧化层的成分、厚度和氧化工艺条件控制减少芯片的内在应力，尤其是氧化后的收缩应力，增加氧化层的原子结合致密度，减缓器件内部侵入的水汽反应。第三，通过外界保护，营造出“气密”封装的效果，如图20所示，可以在芯片外面涂上一定厚度的环氧树脂阻止水汽的腐蚀[25,58-59]。

3.3.4 机械损伤

外界应力造成的裂纹、划痕等损伤会成为位错缺陷形成的源头[32,60]，对于氧化型VCSEL，如上所述，从mesa边缘向内传播的刻痕损伤一直是一个风险[61]。当器件发生机械损伤后，在随后的使用过程中位错缺陷会继续生长，最后引起失效[11]。图21显示了一个刮伤（scratch）如何引起DLD的。左边两张照片显示了划痕的SEM图像，中心图像显示了接收到的失效VCSEL的电致发光(EL)， DLD从左下移动到右上。右边图片显示的是在10 mA下放置几分钟后DLD继续向右生长[11]。

通常，在工艺环节通过严格的100%目检来挑除损伤器件，或者在设计上通过湿法蚀刻出适当宽度的沟槽，或电钝化mesa边缘的材料来避免机械损伤造成的缺陷传到有源区内。

3.4 案例分析

除了上述VCSEL生产设计公司和学术文献的研究成果，本课题组也积累了一定的失效模式案例，包括不同ESD模式冲击后的失效特征，以下加速老化验证过程中3个典型的失效案例作为补充参考。这些失效原因主要包括外延缺陷，氧化异常，mesa氧化应力，ESD和DLD。

(1) 案例1

图22为在高温高电流长时间试验时失效的样品TEM图片，从图中可以看出，其有两个主要的失效特征，一是氧化层边缘有异常氧化问题，二是有源区内有外延黑点缺陷。导致这两个问题的原因分别和氧化工艺和外延生长质量有关。

(2) 案例2

图23为高温高电流500 h老化后失效VCSEL的TEM结果，图片显示了DLD网络图，位错的起源为氧化台面边缘，其在老化过程中逐渐向有源区移动，当位错网络达到一定程度时导致器件失效。如图23（c）XS-TEM结果所示，氧化层在台面边缘较厚，约为100 nm，而氧化尖端厚度约为20 nm，为正常厚度，台面边缘过厚的氧化层会形成较大的应力，成为位错缺陷的源头，是失效的原因。

(3) 案例3

图24的TEM结果为高温高湿（85/85）测试中的失效样品，失效现象为氧化孔边缘出现晶格融化的永久热损伤，在应力最大的氧化边角区域缺陷尤其明显，同时，以氧化孔边缘缺陷为起始点，生成很多DLD网络，这与Krueger的研究结果一致，ESD的失效特征通常伴随DLD位错，ESD损伤后，器件继续工作或者老化，就会在损伤的位置扩散发展为DLD[36]。

4 结束语

氧化型VCSEL的可靠性和器件的材料体系、结构设计、衬底及外延质量、工艺过程和外界因素都有密切关系。在这些因素中，器件的材料体系决定了器件产生缺陷的难易程度，对于GaAs/AlGaAs材料体系的VCSEL来说，较为容易产生位错缺陷；氧化型VCSEL的器件结构中氧化层和蚀刻台面结构引入了固有的缺陷源头，所有失效模式大都和氧化层的应力相关；衬底、外延和器件工艺决定了器件内缺陷的密度水平；外界因素可以引入缺陷的源头，也可提供缺陷产生和扩展增殖的驱动力，其中，VCSEL是ESD敏感型器件，很容易受到ESD的损伤发生失效，而在非气密性应用下湿热腐蚀也是VCSEL失效的一大因素。

本文对导致VCSEL失效的常见模式及其机理进行了总结归纳和分析，并提出对应的改善建议和预防措施。为VCSEL从业人员提供参考，有助于防止失效的产生，或者当问题发生时能够快速有效地确定问题的来源、挖掘出问题的根本原因并实施恰当的改善措施，从而逐步提升器件的应用可靠性、降低使用过程中的失效率，具有重要的实际工程意义。未来需要进一步研究更全面和准确失效原因和机理模型。