Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs∗

Xi-Ming Chen(陈喜明), Bang-Bing Shi(石帮兵), Xuan Li(李轩),Huai-Yun Fan(范怀云), Chen-Zhan Li(李诚瞻), Xiao-Chuan Deng(邓小川),Hai-Hui Luo(罗海辉), Yu-Dong Wu(吴煜东), and Bo Zhang(张波)

1School of Electronic Science and Engineering,University of Electronic Science and Technology of China,Chengdu 610054,China

2State Key Laboratory of Advanced Power Semiconductor Devices,Zhuzhou CRRC Times Semiconductor Company Ltd.,Zhuzhou 412001,China

Keywords: 4H-SiC MOSFET, subthreshold voltage hysteresis, P-type MOS capacitor, density of interface states

1. Introduction

With the developments of silicon carbide (SiC) device processing and substrate crystal growth technique, many issues of SiC metal–oxide–semiconductor field-effect transistors(SiC MOSFETs)have been alleviated,such as low channel mobility, poor reliability and low yield. At present, 4HSiC MOSFETs with voltages rating from 600 V to 1700 V are commercially available from several vendors. Generally speaking, higher power density can be achieved by either increasing the switching frequency of the converter to reduce the sizes of passive components or pushing the operating temperature of the power devices to simplify the cooling system.[1]Hence, 4H-SiC MOSFETs have been promising candidates to further improve the efficiency and power density of power electronic systems,[1]such as main inverter for vehicles,[2]industrial motor drives,[3]and traction converter. Due to the advantages of low power loss, high operating temperature, and high switching frequency.

With the increasing of switching frequency and operating temperature,the gate voltage oscillation of 4H-SiC MOSFET aggravates due to the existence of inevitable parasitic inductance in the package. Meanwhile, the threshold voltage (Vth)of 4H-SiC MOSFET decreases due to the negative temperature coefficient of Vth. When the gate–source voltage (Vgs)spike is higher than the Vth, the fault turn-on case of 4H-SiC MOSFET is triggered. In practical applications, the off-state negative Vgsis expected to be lower, enabling a wider voltage safety margin between Vgsspike and Vthto avoid fault turn-on case of devices. However, when a lower negative Vgsis used as turn-off voltage, there is an obvious subthreshold voltage hysteresis (∆Vth,sub) case in commercial 4H-SiC MOSFEF,[4,5]especially in 4H-SiC trench MOSFET.[6]The∆Vth,subcauses a drain current overshoot at high dV/dt, as the overdrive Vgs–Vthis momentarily higher.[7,8]On the other hand,the ∆Vth,subcauses higher short-circuit peak current and higher energy dissipation during the short-circuit process,especially if a large number of chips is connected in parallel,[9]leading to the degradation of short-circuit withstanding time of 4H-SiC MOSFET.[10]Hence,it is very meaningful to investigate the characteristics and underlying mechanisms of ∆Vth,subin 4H-SiC MOSFETs for higher power density of power electronic systems.

At present, the high-temperature applications of 4H-SiC MOSFETs develop towards 300◦C.[11,12]However, the offstate negative Vgsdependence of Vth,subin 4H-SiC MOSFET at 300◦C has not been studied.[5,13–16]On the other hand,the∆Vth,subof 4H-SiC MOSFET could be caused by the interface traps or oxide traps in channel region.[6,17]As we all know,the commercial 4H-SiC MOSFEFs are n-channel, whose Pwell region is formed by high temperature aluminum ion implantation. Hence, compared with N-type MOS capacitor, Ptype MOS capacitor could be a better choice to investigate the properties of interface trap and gate oxide of 4H-SiC MOSFET.However,the P-type MOS capacitor has never been used to investigate the origin of ∆Vth,subin 4H-SiC MOSFET.

In this paper, the off-state negative Vgsdependence of∆Vth,subis systematically investigated for 4H-SiC planar and trench MOSFET in wide temperature range from 25◦C to 300◦C.Considering the ∆Vth,subphenomenon could be caused by the interface traps or oxide traps in channel region, the Ptype planar and trench MOS capacitors are fabricated following the planar and trench MOSFETs processing,respectively.With the help of P-type planar and trench MOS capacitors,interface traps properties of channel regions in 4H-SiC planar and trench MOSFETs are extracted while underlying mechanisms of ∆Vth,subin the corresponding MOSFETs are investigated.

This paper is organized as follows. In Section 2,the fabrication and measurements of devices are presented briefly.In Section 3, the ∆Vth,subcharacteristics of planar and trench MOSFETs are presented, and the physical mechanisms of∆Vth,subare discussed and analyzed in detail. In Section 4 conclusions are drawn.

2. Experiments and measurements

2.1. Device fabrication

The 4H-SiC planar and trench MOSFETs are fabricated on the N-type,4◦off(0001)oriented,4H-SiC epitaxial wafers using an industrial process. The gate oxide in planar MOSFET is thermally grown in dry oxygen at 1300◦C, and that in trench MOSFET is deposited via chemical vapor deposition, then they are post-annealed in 10% nitric oxide diluted in nitrogen. The thicknesses of fabricated gate oxide in planar and trench MOSFETs are 55 nm and 60 nm,respectively.In this experiment,the P-type planar and trench MOS capacitors are fabricated on the same epitaxial wafers following the processes of planar and trench MOSFETs,respectively.

Fig.1. Schematic cross-sections of the fabricated(a)planar MOSFET,(b)trench MOSFET,P-type(c)planar MOS,and(d)trench MOS capacitors.

In particular,the P-type body regions of P-type MOS capacitors are formed by the high temperature aluminum ion implantation. The gate oxide processes of P-type planar and trench MOS capacitors are the same to that of the corresponding MOSFETs, respectively. In addition, these P-type MOS capacitors undergo the same thermal budgets to the corresponding MOSFETs, including post-implantation hightemperature activation and ohmic contact formation processes.Hence, the P-type planar and trench MOS capacitors can be used to represent the properties of SiO2/SiC interface of channel region in 4H-SiC planar and trench MOSFETs, respectively. The schematic cross-sections of aforementioned devices are shown in Fig.1.

2.2. Device measurement

All the characteristics of devices are measured by using Agilent B1505A device analyzer with cascade MPS150 COAX probe station and temperature controller ATT systems.The off-state negative Vgsdependence of bidirectional drain–source current(Ids)–Vgscharacteristics is evaluated on the planar and trench MOSFET at 25◦C, 150◦C, and 300◦C, respectively. In the measurement of bidirectional Ids–Vgscurves,the up-sweep starts from different off-state negative Vgsto onstate positive Vgs, then returns to the same off-state negative Vgs. During this sweep, the drain voltage (Vd) is 0.1 V, and Vgsis switched by a value of 0.1 V every 100 ms for the Vgssweep. The ∆Vth,subis extracted from the bidirectional Ids–Vgscurves as shown in Fig.2. Here,the Vth,subis defined as Vgsat Ids=10 nA.

Fig.2. Bidirectional Ids–Vgs curves of 4H-SiC trench MOSFET at 25 ◦C.

The capacitance–voltage(C–V)hysteresis caused by negative gate voltage bias is evaluated on the P-type planar and trench MOS capacitor at 25◦C and 300◦C,respectively. The tested frequency is 100 kHz. The gate voltage starts from−25 V to 10 V, then returns to −25 V. The distribution of density of interface states (Dit) in bandgap are extracted by high-low method at different temperatures. As the paper[18]reported, the distribution of Ditnear valence band (Ev) can be determined at 25◦C while that near middle bandgap can be determined at 300◦C. The high frequency (100 kHz) and quasi-static C–V (QSCV) curves of P-type planar and trench MOS capacitors are measured at 25◦C and 300◦C, and the sweep direction of C–V is from accumulation to depletion.

3. Results and discussion

3.1. ∆Vth,sub characteristics of planar and trench MOSFETs

The off-state negative Vgsdependences of ∆Vth,subat 25◦C, 150◦C, and 300◦C are shown in Fig.3. For planar MOSFET, the maximum ∆Vth,subis −0.25 V, −0.12 V,and −0.05 V at 25◦C, 150◦C, and 300◦C, respectively.For trench MOSFET, the maximum ∆Vth,subis −3.0 V,−3.1 V, and −2.6 V at 25◦C, 150◦C, and 300◦C, respectively. Compared with planar MOSFET, the trench MOSFET shows larger ∆Vth,subat 25◦C, 150◦C, and 300◦C. In addition, whether it is planar or trench MOSFET, the maximum ∆Vth,subdecreases with temperature increasing from 25◦C to 300◦C. On the other hand, it is obvious that the minimum saturation negative Vgsof ∆Vth,subin trench MOSFET is lower than that of planar MOSFET. Meanwhile, whether it is planar or trench MOSFET, the minimum saturation negative Vgsof ∆Vth,subdecreases with temperature increasing from 25◦C to 300◦C. When the operating temperature is ranging from 25◦C to 300◦C and ∆Vth,subis less than 0.1 V,the off-state negative Vgsof planar and trench MOSFETs should be above −4 V and −2 V,respectively. In other words,in order to alleviate ∆Vth,sub,the off-state negative Vgsof planar MOSFET is accepted above −4 V while trench MOSFET above −2 V.

Fig.3. Dependence of ∆Vth,sub of SiC MOSFETs on off-state negative Vgs at different temperatures: (a)planar MOSFETs,(b)trench MOSFETs.

3.2. C–V hysteresis of planar and trench MOS capacitor

The measured C–V hysteresis caused by negative gate voltage bias is shown in Fig.4. When the C–V sweep is from−25 V to 10 V,there is a shift toward the negative direction in the C–V curves. It is indicated that the holes are captured at negative gate voltage stress bias,which affect actually the net charge of the MOS system. Because the voltage sweep is too fast for interface to reach the thermodynamic equilibrium.[5]As a result,a measurable C–V hysteresis appears in the P-type MOS capacitor. Compared with planar MOS capacitor, the trench MOS capacitor shows larger C–V hysteresis at 25◦C and 300◦C.As figure 3 shows,the maximum ∆Vth,subin trench MOSFET is also larger than that in planar MOSFET.Thus,it is confirmed that the tendency for C–V hysteresis to occur depending on the gate oxide of the P-type MOS capacitor is in accord with maximum ∆Vth,subof the corresponding MOSFET.It is indicated that the P-type MOS capacitor can be utilized to instead of 4H-SiC MOSFET to investigate the ∆Vth,subproperties. On the other hand,with the temperature increasing from 25◦C to 300◦C,the C–V hysteresis decreases in trench MOS capacitor. It is indicated that the net charge at the SiO2/SiC interface can reach easily thermodynamic equilibrium due to the decrease of emission constant time of trapped hole. This tendency is also similar to maximum ∆Vth,subin trench MOSFET.

Fig.4. High frequency (100 kHz)C–V cycle curves of P-type MOS capacitors at 25 ◦C and 300 ◦C: (a)–(b) planar MOS capacitor, (c)–(d)trench MOS capacitor.

3.3. Traps distribution at SiO2/SiC interface

The high frequency (100 kHz)C–V and QSCV at 25◦C and 300◦C are shown in Fig.5. Whether it is P-type planar or trench MOS capacitor, the C/Coxvalue at 100 kHz is lower than that of the quasi-static one. It could be explained by that the holes are trapped at starting negative gate voltage bias and functioned as series resistance to the MOS capacitor. With the C–V frequency increasing from quasi-static to 100 kHz, the series resistance shows more obvious influence on the C/Coxvalue. Whether it is 25◦C or 300◦C, the different C/Coxbetween 100 kHz and quasi static (∆C/Cox) in the trench MOS capacitor is larger than that in the planar one.It is indicated that more holes are trapped in the trench MOS capacitor at negative gate voltage bias. Whether it is planar or trench MOS,the ∆C/Coxvalue decreases with temperature increasing from 25◦C to 300◦C.It could be explained by that the emission constant times of trapped holes near Evdecrease with the increase of temperature. The emission constant time for trapped hole from an interface state to the Evin a P-type semiconductor can be written as[18]

where σpis the capture cross section for hole, υTis the thermal velocity, Nvis the effective density of states in the Ev, κ is Boltzmann’s constant, T is the absolute temperature, and E −Evis the energy of the interface state relative to the Ev.With the temperature increasing form 25◦C to 300◦C, the τpfor trapped hole decreases so that a part of trapped holes near the Evis fast enough emitted into Evduring high frequency (100 kHz) C–V sweep. Consequently, less trapped holes are functioned as series resistance, resulting in the decrease of ∆C/Cox.

The distribution of Ditis extracted by using high-low method at different temperatures,as shown in Fig.6. The Ditin SiO2/4H-SiC interface is about two orders higher than that in SiO2/Si interface. On the other hand, the bandgap of 4HSiC is 3.26 eV,which is three times wider than that of silicon.As equation(1)described,the interface traps near the middle bandgap of 4H-SiC have longer emission constant time than that of silicon. Consequently, when 4H-SiC MOSFET is at the off-state negative Vgsbias, more holes are trapped so that the inversion charge in the channel is temporarily enhanced before being gradually neutralized. It could be the root cause of the obvious ∆Vth,subphenomenon of 4H-SiC MOSFET.Compared with the planar MOS capacitor, trench MOS capacitor shows one order of magnitude higher Ditin the energy level range from 1.63 eV to 3 eV.Therefore,the maximum ∆Vth,subof trench MOSFET is larger than that of planar MOSFET.The maximum ∆Vth,subcan be written as[7]

Fig.5. High frequency(100 kHz)and quasi static C–V curves of P-type MOS capacitors at 25 ◦C and 300 ◦C:(a)–(b)planar MOS capacitor,(c)–(d)trench MOS capacitor.

Fig.6. Dit as a function of the energy on P-type MOS capacitors: (a)planar MOS capacitor,(b)trench MOS capacitor.

4. Conclusion

In this paper, the characteristics and mechanisms of∆Vth,subare investigated for 4H-SiC planar and trench MOSFETs. Compared with planar MOSFEF, trench MOSFET shows larger ∆Vth,subin the temperature range from 25◦C to 300◦C.Furthermore,whether it is planar or trench MOSFET,both maximum ∆Vth,suband corresponding saturation negative Vgsdecreases with temperature increasing from 25◦C to 300◦C. In order to alleviate the effect of ∆Vth,subon normal operation,the off-state negative Vgsof planar and trench MOSFET should be above −4 V and −2 V, respectively. Furthermore, it is confirmed that the tendency for C–V hysteresis to occur depending on the gate oxide of the P-type MOS capacitor is in accord with maximum ∆Vth,subof the corresponding MOSFET.The obvious ∆Vth,subof 4H-SiC MOSFET is caused by the high density of hole interface traps between Eiand Ev.The maximum ∆Vth,subof trench MOSFET is about twelve times larger than that of planar MOSFET, owing to the one order of magnitude higher Dit. In order to improve the ∆Vth,subof 4H-SiC MOSFET, the high Ditbetween Eiand Evshould be further improved,especially in 4H-SiC trench MOSFET.