目录
- Reconfigurable computing: a promising microchip architecture for artificial intelligence
- Architecture, challenges and applications of dynamic reconfigurable computing
- A survey of FPGA design for AI era
- A survey of neural network accelerator with software development environments
- Accelerating hybrid and compact neural networks targeting perception and control domains with coarse-grained dataflow reconfiguration
- HRM: H-tree based reconfiguration mechanism in reconfigurable homogeneous PE array
- Towards efficient deep neural network training by FPGA-based batch-level parallelism
- Towards high performance low bitwidth training for deep neural networks
- A routing algorithm for FPGAs with time-multiplexed interconnects
- Optimizing energy efficiency of CNN-based object detection with dynamic voltage and frequency scaling